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| BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW PRODUCT OVERVIEW S3C24A0 AN APPLICATION PROCESSOR FOR 2.5G/3G MOBILE PHONES SOC R&D CENTER SAMSUNG ELECTRONICS CORP. 1-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR CONTENTS CH1. INTRODUCTION CH2. SROM CH3. SDRAM CH4. NAND CH5. BUS MATRIX CH6. INTERRUPT CH7. PWM TIMER CH8. WATCH DOG TIMER CH9. DMA CH10. RTC CH11. UART CH12. IRDA CH13. IIC CH14. IIS CH15. SPI CH16. AC97 CH17. USB HOST CH18. USB DEVICE CH19. MODEM CH20. GPIO CH21. CAMERA CH22. MPEG4-OVERVIEW CH23. MOTION ESTIMATION CH24. MOTION COMPENSATION CH25. DCTQ CH26. VLX CH27. POST CH28. LCD CH29. KEYPAD CH30. ADC & TOUCH CH31. SD/MMC CH32. MEMORY STICK CH33. CLOCK & POWER CH34. MECHANICAL DATA 1-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW 1 INTRODUCTION (PRELIMINARY) 1.1 ARCHITECTURAL OVERVIEW The S3C24A0 is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, low power, and high performance micro-controller solution for mobile phones and general applications. To provide a sufficient H/W performance for the 2.5G & 3G communication services, the S3C24A0 adopts dual-32-bit bus architecture and includes many powerful hardware accelerators for the motion video processing, serial communications, and etc. For the real time video conferencing, an optimized MPEG4 H/W Encoder/Decoder is integrated. To reduce total system cost and enhance overall functionality, the S3C24A0 also includes following components: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (TFT), Camera Interface, MPEG-4 ME, MC, DCTQ, NAND Flash Boot loader, System Manager (power management & etc.), SDRAM controller, 2-ch UART, 4-ch DMA, 4-ch Timers, General I/O Ports, IIC-BUS interface, USB Host, SD Host & Multi-Media Card Interface, Memory Stick Interface, PLL for clock generation & etc. The S3C24A0 can be used as a most powerful Application Processor for mobiles phones. For this application, the S3C24A0 has a Modem Interface to communicate with various Modem Chips. The S3C24A0 is developed using an ARM926EJ-S core, advanced 0.13um CMOS standard cells and memory compliers. Its low-power, simple, elegant and fully static-design scheme is particularly suitable for cost-sensitive and power-sensitive applications. Also, the S3C24A0 adopts a de-facto standard bus architecture - the AMBA (Advanced Microcontroller Bus Architecture). One of outstanding features of the S3C24A0 is its CPU core, a 16/32-bit ARM926EJ-S RISC processor designed by ARM, Ltd. The ARM926EJ-S is a single chip MCU and Java enabled microprocessor. The ARM926EJ-S also implements the MMU, the AMBA BUS, and the Harvard cache architecture with separate 16KB instruction and 16KB data caches, each cache with an 8-word line length. By providing a complete set of common system peripherals, the S3C24A0 minimizes overall system costs and eliminates the need to configure additional components. 1.2 FEATURES This section summarizes the features of the S3C24A0. Figure 1-1 is an overall block diagram of the S3C24A0. 1.2.1 Microprocessor and Overall Architecture * * * * * SoC (System-on-Chip) for mobile phones and general embedded applications. 16/32-Bit RISC architecture and powerful instruction set with ARM926EJ-S CPU core. ARM's Jazelle Java technology Enhanced ARM architecture MMU to support WinCE, Symbian and Linux Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance 1-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR * * * * * * * * 4 way set-associative cache with I-Cache (16KB) and D-Cache (16KB). 8-words per line with one valid bit and two dirty bits per line Pseudo random or round robin replacement algorithm. Write through or write back cache operation to update the main memory. The write buffer can hold 16 words of data and four addresses. ARM926EJ-S core supports the ARM debug architecture Internal AMBA (Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB) Dual AHB bus for high-performance processing (AHB-I & AHB-S) 1.2.2 Memory Subsystem * * * * * * High bandwidth Memory subsystem with two access channels (accesses from two AHB buses) and threechannel memory ports Double the bandwidth with the simultaneous access capability ROM/SRAM/NOR-Flash/NAND-Flash channel One SDRAM channels Up to 1GB Address space Low-power SDRAM interface support : Mobile SDRAM function DS : Driver Strength Control TCSR : Temperature Compensated Self-Refresh Control PASR : Partial Array Self-Refresh Control * NAND Flash Boot Loader with the ECC circuitry to support booting from NAND Flash 4KB Stepping Stone Support 1G, 2G bit NAND Flash 1.2.3 General Peripherals * Interrupt Controller 61 Interrupt sources (1 Watch Dog Timer, 5 Timer, 6 UART, 18 External Interrupts, 4 DMA, 2 RTC, 3 ADC, 1 I2C, 1 AC97, 1 NAND Flash, 1 IrDA, 1 Memory Stick, 2 SPI, 1 SDI, 2 USB (Host and Device), 1 Keypad, 1 Modem Interface, 2 Camera Interface, 4 MPEG, 2 LCD, 1 Battery Fault, 1 Post) Level/Edge mode on external interrupt source. Programmable polarity of edge and level. Supports FIQ (Fast Interrupt request) for very urgent interrupt request. Timer with PWM (Pulse Width Modulation) 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation Programmable duty cycle, frequency, and polarity Dead-zone generation. Support external clock source. * 1-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW * 16-bit Watchdog Timer. Interrupt request or system reset at time-out. 4-ch DMA controller. Support memory to memory, IO to memory, memory to IO, and IO to IO Burst transfer mode to enhance the transfer rate. RTC (Real Time Clock) Full clock feature: msec, sec, min, hour, day, date, week, month, year. 32.768 KHz operation Alarm interrupt Time-tick interrupt * * 1.2.4 Serial Communication * UART 2-channel UART with DMA-based or interrupt-based operation Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive Supports external clock for the UART operation (XuCLK) Programmable baud rate Supports IrDA 1.0 Loop back mode for testing Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO IrDA Support IrDA 1.1 (1.152Mbps and 4Mbps) Support FIFO operation in the MIR and FIR mode Configurable FIFO Size (16-byte or 64-byte) Support Back-to-Back Transactions Support Software Selection Temic-IBM or HP Transceiver Support Little-endian access IIC-Bus Interface 1-ch Multi-Master IIC-Bus Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in the standard mode IIS-Bus Interface 1-ch IIS-bus for the audio-codec interface with DMA-based operation Serial, 8/16-bit per channel data transfers 128 Bytes (64-Byte + 64-Byte) FIFO for receive/transmit Supports IIS format and MSB-justified data format * * * 1-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR * SPI Interface 2-ch Serial Peripheral Interface Protocol version 2.11 compatible 2x8 bits Shift register for receive/transmit. DMA-based or interrupt-based operation. AC97 Audio-CODEC Interface 48KHz 16-bit sampling 1-ch stereo PCM inputs / 1-ch stereo PCM outputs / 1-ch MIC input USB Host 2-port USB Host Complies with OHCI Rev. 1.0 Compatible with the USB Specification version 1.1 USB Device 1-port USB Device 5 End-points for USB Device Compatible with the USB Specification version 1.1 * * * 1.2.5 Parallel Communication * Modem Chip Interface 8-bit Asynchronous SRAM interface-style interface On-chip 2KB dual-ported SRAM buffer Interrupt Request for Data Exchange Programmable Interrupt Port Address 32-bit GPIO Fully configurable 32-bit GPIO * 1.2.6 Image and Video Processing * Camera Inteface ITU601/ITU656 YCbCr 4:2:2 8/16-bit mode Image down scaling capability for variable applications Digital Zoom-In Image X, Y-flip, 180 rotation Input Image Window Cut Two master for dedicated DMA operation Programmable burst length for DMA operation Programmable polarity of video sync signals Wide horizontal line buffer (maximum 2048 pixel) 1-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW - Up to 4M pixel resolution support for scaled image (image preview or motion video capturing) and 16M pixel for unscaled image (JPEG) * Format conversion from YCrCb 4:2:2 to 4:2:0 for codec, and to RGB 4:4:4 for preview Hardware Accelerated MPEG4 Video Encoding/Decoding * A AHB Interface Realtime MPEG-4 Video Encoding & Decoding Up to Simple Profile at Level 3 (352x288 at 30fps) Supports H.263 Base Line MPEG-4 ME (Motion Estimation) * Highly optimized hard-wired engine Unrestricted Mode and Advanced Prediction Mode (4MV) Use the advanced MRMCS algorithm Half-pel search Programmable Image size up to 2048x2048 Padding for Macro-block basis Search Range : [-16, 15.5] Intra/Inter Mode Decision MC (Motion Compensation) MC (Motion Compensation) * Highly optimized hard-wired engine Unrestricted Mode and Advanced Prediction Mode (4MV) Half-pel search Programmable Image size up to 2048x2048 Dedicated DMA Macroblock-based Pading Search Range : [-64, 63.5] DCTQ - DCT/IDCT/Q/IQ operations*AMBA AHB Interface Support MPEG-4 Simple Profile Level 3 / H.263 Base-Line*Support programmable image size up to 4096x4096 Macroblock-based processing Rate Control by Qp Information Local DMA Support MPEG-4 Encoding / Decoding Support JPEG DCT / IDCT Operation Operation unit : 1MB(MacroBlock) ~ 1 Frame 1-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR * VLX VLC/VLD operations AMBA AHB Interface Support MPEG4 Simple Profile Level 3/ H.263. Baseline Macro block-based processing Dedicated DMA Only DCTQ coefficient VLC/VLD operation Only DC prediction operation in VLC Post Processor Dedicate DMA with Offset Address 3 Channel Scaling Pipelines for Video/Graphis Signal Input Format : YCbCr4:2:0, YCbCr4:2:2, or RGB 16b/24b Output Format : RGB 16b/24b Programmable Image Size (Source up to 4096x4096, Destination up to 2048x2048) Programmable Scale Ratio (Up-scale: up to Max. Destination Size, Down-scale: ~>1/64 in X & Y) Format Conversion for Video Signal (YCbCr4:2:0 or YCbCr4:2:2) Color Space Conversion (YCbCr2RGB) Separate Processing Clock from AHB Interface Clock * 1.2.7 Display Control * TFT LCD Interface 18-bit Parallel or 6bit*3 Interface 1/2/4/8-bpp Palletized or 8/16/18-bpp Non-Palletized Color-TFF support Supports 640x480, 320x240, 176x192 and others Up to 16 Mbyte virtual screen size Supports Multiple Virtual Display Screen (Supports Hardware Horizontal/Vertical Scrolling) Programmable timing control for different display panels Dual Buffer OSD (On Screen Display) Realtime overlay plane multiplexing Programmable OSD window positioning Per-pixel alpha blending for 18-bpp OSD images Fixed alpha-value for 8-/16-/18-bpp OSD image 256-level alpha blending 24-bit color key support Dual buffer * 1-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW 1.2.8 Input Devices * Keypad Interface Provides internal debouncing filter 5-input, 5-output pins for key scan in/out A/D Converter and Touch Screen Interface 8-ch multiplexed ADC Max. 500K samples/sec and 10-bit resolution * 1.2.9 Storage Devices * SD Host Compatible with SD Memory Card Protocol version 1.0 Compatible with SDIO Card Protocol version 1.0 64 Bytes FIFO for Tx/Rx DMA based or Interrupt based operation Compatible with Multimedia Card Protocol version 2.11 Memory Stick Host Memory Stick version 1.3 compliant * 1.2.10 System Management * * Little Endian format support System operating clock generation Two on-chip PLLs, MPLL & UPLL MPLL generates the system reference clock, 200MHz@1.2V UPLL generates clocks for the USB Host/Device, IrDA and Camera Power Management Clock-off control for individual components Various power-down modes are available such as IDLE, STOP and SLEEP Wake-up by one of external interrupts or by the RTC alarm interrupt, etc. * 1.2.11 Electrical Characteristics * Operating Conditions - Supply Voltage for Logic Core: 1.25V +/- 0.05V - External Memory Interface: 1.8V / 2.5V / 3.3V - External I/O Interface: 3.3V Operational Frequency - Max. 200MHz@1.25V * 1-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR 1.2.12 Package * 337-pin FBGA (0.5mm pitch, 13mm x 13mm) 1-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW TIMER*5 Camera Interface DCTQ/VLX ME/MC Memory Controller SDRAM Memory Controller SRAM/NOR/NAND /ROM Postprocessor USB1.1 Device AHB-I AHB to AHB Bridge AHB to APB Bridge Memory Stick Host SD Host AHB-S Inst. Data USB 1.1 Host A P B INTC NAND Boot Loader UART*2 ARM926EJ I2C/I2S/S PI IrDA1.1 Modem Interface 4-Channel DMA System/Power Down Controller GPIO*32 S3C24A0 RISC MICROPROCESSOR 10-bit ADC/Touch Screen KEYPAD Figure 1- 1 An Overall Block Diagram of the S3C24A0 Digital Display Controller TFT LCD Interface Audio Codec IF Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. MPEG4 H/W Accelerator Watch Dog Timer 1-11 BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR 1.3.2 Pin Assignment #A1 INDEX MARK 337-Pin FBGA Pin Assignment 1-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW Table 1-1. 337-Pin FBGA Pin Assignments - Pin Number Order Pin Number A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 Pin Name XCIYDATA[4] VSS_B XCICDATA[0] XCIYDATA[7] XCIPCLK XVVD[5] XVVD[7] XVVCLK XVDEN XCICDATA[7] XRDATA[0] XRDATA[5] XRADDR [3] XRADDR [7] XRNWBE[1] XRDATA[8] XRDATA[13] XRADDR [10] XRADDR [16] XRADDR [17] XRADDR[20] XRADDR [23] XFRNB[0] XJTCK XCIYDATA[0] XCIYDATA[2] XCIYDATA[6] XCICDATA[2] XCICDATA[3] XVVD[11] XVVD[15] XVVD[18] XVVD[21] Pin Number B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 Pin Name XRDATA[1] XRDATA[3] XRDATA[7] XRADDR[5] XRNWBE[0] XRWEN XRCSN[2] XRDATA[14] XRADDR[11] XRADDR[15] XRADDR[22] XFALE XFNFACYC XJTMS XJTRSTN XCICLK XCICDATA[1] XVVD[4] XCIHREF XCICDATA[4] XCICDATA[6] XVHSYNC XVVD[20] XVVD[23] VDD_C XRDATA[6] XRADDR[1] XRADDR [6] XRWAITN XRCSN[1] XRDATA[10] XRDATA[12] XRADDR [9] Pin Number C21 C22 C23 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E01 E02 E03 E04 E20 E21 E22 Pin Name XRADDR [21] XFNFPS XFNFADV XJTDO XJTDI XVVD[2] XCIRSTN XCIYDATA[5] XCIVSYNC XVVD[13] XVVD[14] XCICDATA[5] XJRTCK XVVSYNC XVVD[19] XVVD[22] XRADDR [4] XRADDR [2] XRADDR [0] XRADDR [14] XRADDR [19] XFCLE XRADDR [8] XRADDR [12] XFNFBW XRADDR [25] XGPIO[31] X2CSDA X2CSCL XCIYDATA[1] XFRNB[1] XRADDR [24] XPDATA[2] 1-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR Table 1-1. 337-Pin FBGA Pin Assignments - Pin Number Order Pin Number E23 F01 F02 F03 F04 F20 F21 F22 F23 G01 G02 G03 G04 G20 G21 G22 G23 H01 H02 H03 H04 H20 H21 H22 H23 J01 J02 J03 J04 J11 J12 J13 J20 Pin Name XPDATA[1] XGPIO[28] XGPIO[29] XGPIO[30] XCIYDATA[3] XRADDR [18] XPDATA[0] XPDATA[6] XPDATA[3] XGPIO[24] XGPIO[26] XGPIO[27] XVVD[3] XRADDR [13] XPDATA[5] XPDQM[0] XPDATA[7] XGPIO[20] XGPIO[23] XGPIO[22] XVVD[6] XPDATA[4] VDD_D XPDQM[1] XPDQM[2] XGPIO[17] XGPIO[18] XGPIO[25] XVVD[10] VSS_B VSS_E VDD_E XRDATA[15] Pin Number J21 J22 J23 K01 K02 K03 K04 K11 K12 K13 K20 K21 K22 K23 L01 L02 L03 L04 L09 L10 L11 L12 L13 L14 L15 L20 L21 L22 L23 M01 M02 M03 M04 Pin Name VDD_A XPDQM[3] XPDATA[8] XGPIO[11] XGPIO[14] XGPIO[16] XVVD[12] VDD_B VSS VSS_E XRDATA[11] XPDATA[9] XPDATA[10] XPDATA[11] XGPIO[7] XGPIO[10] XGPIO[12] XGPIO[21] VDD_C VDD_C VSS VSS VSS VDD_E VSS_D XPDATA[14] XPDATA[12] XPDATA[13] XPADDR[0] XGPIO[0] XGPIO[6] VDD_B XGPIO[19] Pin Number M09 M10 M11 M12 M13 M14 M15 M20 M21 M22 M23 N01 N02 N03 N04 N09 N10 N11 N12 N13 N14 N15 N20 N21 N22 N23 P01 P02 P03 P04 P11 P12 P13 Pin Name VSS_B VDD_F VSS VSS VSS VDD_A VSS_D XPADDR[2] XPDATA[15] XPADDR[1] XPADDR[3] X97SYNC X97RESETN XGPIO[4] XGPIO[8] VDD_A VDD_B VSS VSS VSS VSS_D VDD_D XRDATA[9] XPADDR[4] XPADDR[5] XPADDR[6] XURTSN X97SDO X97BITCLK XGPIO[5] VSS_B VDD_F VSS_D 1-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW Table 1-1. 337-Pin FBGA Pin Assignments - Pin Number Order Pin Number P20 P21 P22 P23 R01 R02 R03 R04 R11 R12 R13 R20 R21 R22 R23 T01 T02 T03 T04 T20 T21 T22 T23 U01 U02 U03 U04 U20 U21 U22 U23 V01 V02 Pin Name XRCSN[0] XPDATA[16] XPADDR[7] XPDATA[18] XGTMODE[2] XURXD XGPIO[2] XGPIO[15] VDD_A VDD_B VSS_D XROEN XPDATA[17] XPDATA[19] XPSCLK X2SCDCLK XUCTSN X97SDI XGPIO[13] XPDATA[24] XPDATA[20] XPDATA[21] XPDATA[23] X2SDO X2SLRCK XUTXD XGPIO[9] XRDATA[4] XPDATA[22] XPCKE XPRASN XSPIMOSI XSPISSIN[1] Pin Number V03 V04 V20 V21 V22 V23 W01 W02 W03 W04 W20 W21 W22 W23 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Pin Name XGTMODE[3] XUCLK XRDATA[2] XPDATA[29] XPWEN XPCASN XGTMODE[1] XSPIMISO XSPISSIN[0] X2SCLK VDD_D VDD_A XPCSN[0] XPCSN[1] XSWRESETN XGTMODE[0] XSPICLK X2SDI XGBATFLTN XGPIO[1] XGPIO[3] VDD15 XSRSTOUTN XUDDP XSDDAT[3] VDD20(VDDpadUSB) XMSSDIO XMSPI XMICSN XMIADR[10] XPADDR[13] XMIADR[4] XMIADR[2] Pin Number Y20 Y21 Y22 Y23 AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB01 AB02 AB03 AB04 AB05 AB06 Pin Name VDD_D XPDATA[25] XPDATA[27] XPDATA[26] XRTCXTI XGREFCLKSEL[0] XGPWROFFN XADCAIN[5] XADCAVREF XADCAIN[2] GND10 VDD13 XSRESETN XSXTOUT XUSDP[0] XUSDN[0] XMSBS XMIWEN XMIADR[8] XMIADR[6] XMIDATA[6] VDD_A XMIDATA[2] XMIADR[0] VDD_D XPDATA[31] XPDATA[28] VDD10 XADCAIN[7] XRTCXTO XGREFCLKSEL[1] XADCAIN[0] VDD11 1-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR Table 1-1. 337-Pin FBGA Pin Assignments - Pin Number Order Pin Number AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 Pin Name GND12 XSUPLLCAP XSEXTCLK XUSDP[1] XUDDN XSDDAT[1] GND19(VSSpadUSB) XMIOEN XMIADR[7] XMIDATA[7] XMIDATA[4] XMIIRQN XMIDATA[0] XMIADR[1] Pin Number AB21 AB22 AB23 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 Pin Name XPADDR[11] XPDATA[30] XPADDR[8] GND9(VSSrtc) XADCAIN[6] XADCAIN[4] XADCAIN[3] XADCAIN[1] XSMPLLCAP GND14 XGMONHCLK XSXTIN XUSDN[1] XMSSCLKO Pin Number AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 Pin Name XSDDAT[2] XSDDAT[0] XMIADR[9] XMIADR[5] XMIDATA[5] XMIDATA[3] XMIDATA[1] XMIADR[3] XPADDR[14] XPADDR[12] XPADDR[10] XPADDR[9] 1-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Pin Number Name Default Function I/O Cell Type (24A0A) P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P AA7 AB7 AC7 AB13 AC1 AA18 J21 M14 N9 R11 W21 K11 M3 N10 R12 C12 L10 L9 AA21 H21 N14 N15 W20 Y20 J13 L14 M10 P12 AB1 AB6 AA8 Y8 Y12 K12 L11 L12 L13 VSSadc VSSMpll VSSUpll VSSpadUSB VSSrtc VDDlogic VDDlogic VDDlogic VDDlogic VDDlogic VDDlogic VDDpadIO VDDpadIO VDDpadIO VDDpadIO VDDarm VDDarm VDDarm VSSadc VSSMpll VSSUpll VSSpadUSB VSSrtc VDDlogic VDDlogic VDDlogic VDDlogic VDDlogic VDDlogic VDDpadIO VDDpadIO VDDpadIO VDDpadIO VDDarm VDDarm VDDarm P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P VDDpadSDRAM VDDpadSDRAM VDDpadSDRAM VDDpadSDRAM VSS VSS VDDpadSDRAM VDDpadSDRAM VDDpadSDRAM VDDpadSDRAM VDDpadSDRAM VDDpadSDRAM VDDpadFlash VDDpadFlash VDDalive VDDalive VDDrtc VDDadc VDDMpll VDDupll VDDpadUSB VSS VSS VSS VSS VDDpadFlash VDDpadFlash VDDalive VDDalive VDDrtc VDDadc VDDMpll VDDupll VDDpadUSB VSS VSS VSS VSS 1-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp P P P P P P P P P P P P P P P P I/H I/H H or L/L L/L/L I L/L H/L/L I L/L I L/L L/L I I I P P P P P P P P P P P P P P P P L or I L or I Hi-z or H or L H or L or I Hi-z or H or L H or L or I Hi-z or H or L Hi-z or H or L Hi-z or H or L P P P P P P P P P P P P P P P P H H H L L Pre H L L - Pin Number Name Default Function I/O Cell Type (24A0A) P P P P P P P P P P P P P P P P phbsud8sm phbsud8sm phot8 phbsu100ct8sm phisu phot8 phbsu100ct8sm phis phot8 phisu phot8 phot8 phiar10_abb phiar10_abb phiar10_abb M11 M12 M13 N11 N12 N13 A2 J11 M9 P11 L15 M15 P13 R13 J12 K13 E3 E2 T1 W4 Y4 U1 U2 P3 N2 T3 P2 N1 AB5 AC5 AA6 VSS VSS VSS VSS VSS VSS VSSpadIO VSSpadIO VSSpadIO VSSpadIO VSS VSS VSS VSS VSS VSS VSSpadIO VSSpadIO VSSpadIO VSSpadIO P P P P P P P P P P P P P P P P I/O I/O O I/O I O I/O I O I O O Ain Ain Ain VSSpadSDRAM VSSpadSDRAM VSSpadSDRAM VSSpadSDRAM VSSpadSDRAM VSSpadSDRAM VSSpadSDRAM VSSpadSDRAM VSSpadFlash VSSpadFlash X2cSCL X2cSDA X2sCDCLK X2sCLK X2sDI X2sDO X2sLRCK X97BITCLK X97RESETn X97SDI X97SDO X97SYNC XadcAIN[0] XadcAIN[1] XadcAIN[2] VSSpadFlash VSSpadFlash X2cSCL X2cSDA X2sCDCLK X2sCLK X2sDI X2sDO X2sLRCK X97BITCLK X97RESETn X97SDI X97SDO X97SYNC XadcAIN[0] XadcAIN[1] XadcAIN[2] 1-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp I I I I I I I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L L/L I I L/L I I I I I I I I I L/L L/L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L L Pre L L Pin Number Name Default Function I/O Cell Type (24A0A) AC4 AC3 AA4 AC2 AB2 AA5 A3 C4 B5 B6 C7 D9 C8 A10 C3 C6 A5 D4 D6 B2 E4 B3 F4 A1 D5 B4 A4 B22 D19 XadcAIN[3] XadcAIN[4] XadcAIN[5] XadcAIN[6] XadcAIN[7] XadcAVREF XciCDATA[0] XciCDATA[1] XciCDATA[2] XciCDATA[3] XciCDATA[4] XciCDATA[5] XciCDATA[6] XciCDATA[7] XciCLK XciHREF XciPCLK XciRSTn XciVSYNC XciYDATA[0] XciYDATA[1] XciYDATA[2] XciYDATA[3] XciYDATA[4] XciYDATA[5] XciYDATA[6] XciYDATA[7] XfALE XfCLE XadcAIN[3] XadcAIN[4] XadcAIN[5] XadcAIN[6] XadcAIN[7] XadcAVREF XciCDATA[0] XciCDATA[1] XciCDATA[2] XciCDATA[3] XciCDATA[4] XciCDATA[5] XciCDATA[6] XciCDATA[7] XciCLK XciHREF XciPCLK XciRSTn XciVSYNC XciYDATA[0] XciYDATA[1] XciYDATA[2] XciYDATA[3] XciYDATA[4] XciYDATA[5] XciYDATA[6] XciYDATA[7] XfALE XfCLE Ain Ain Ain Ain Ain Ain I I I I I I I I O I I O I I I I I I I I I O O phiar10_abb phiar10_abb phiar10_abb phiar10_abb phiar10_abb phia_abb phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phot12sm phis phis phot8 phis phis phis phis phis phis phis phis phis phot8 phot8 1-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP I/O En(L)=>output mode mode PullupEn(L)=>PullU p I I I I I I I I I I I I I H L/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L Hi-z or H or L H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I L - Pin Number Name Default Function Cell Type (24A0A) B23 C23 D22 C22 A23 E20 Y5 AC8 M1 Y6 L2 K1 L3 T4 K2 R4 K3 J1 J2 M4 R3 H1 L4 XfNFACYC XfNFADV XfNFBW XfNFPS XfRnB[0] XfRnB[1] XgBATFLT XgMONHCLK XgpIO[0]/EINT0 XgpIO[1]/EINT1 XgpIO[10]/YMON XgpIO[11]/EINT11 XgpIO[12]/EINT12/XMON XgpIO[13]/EINT13/XPON XgpIO[14]/EINT14/RTC_ALMINT XgpIO[15]/EINT15/XspiMOSI XgpIO[16]/EINT16/XspiMISO XgpIO[17]/EINT17/XspiCLK XgpIO[18]/EINT18/XkpROW0 XgpIO[19]/PWM_ECLK/XkpROW 1 XgpIO[2]/EINT2/PWM_TOUT0 XgpIO[20]/PWM_TOUT0/ XkpROW2 XgpIO[21]/PWM_TOUT1/ XkpROW3 XfNFACYC XfNFADV XfNFBW XfNFPS XfRnB[0] XfRnB[1] XgBATFLT phis phis phis phis phisu phisu phis phot8 phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m XgMONHCLK O XgpIO[0] XgpIO[1] I/O I/O XgpIO[10] I/O XgpIO[11] I/O XgpIO[12] I/O XgpIO[13] I/O XgpIO[14] I/O XgpIO[15] I/O XgpIO[16] I/O XgpIO[17] I/O XgpIO[18] I/O XgpIO[19] I/O XgpIO[2] I/O XgpIO[20] I/O XgpIO[21] I/O 1-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP Default Function I/O En(L)=>output mode mode PullupEn(L)=>PullU p XgpIO[22] XgpIO[23] XgpIO[24] XgpIO[25] XgpIO[26] XgpIO[27] XgpIO[28] XgpIO[29] XgpIO[3] XgpIO[30] XgpIO[31] XgpIO[4] XgpIO[5] XgpIO[6] XgpIO[7] XgpIO[8] XgpIO[9] XgPWROFFn I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L H H H H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I L H - Pin Number Name Cell Type (24A0A) XgpIO[22]/PWM_TOUT2/XkpROW4 H3 XgpIO[23]/PWM_TOUT3/XkpCOL0 H2 G1 J3 G2 G3 XgpIO[28]/XuCTSn1/RTC_ALMINT F1 XgpIO[29]/XuRTSn1/IrDA_SDBW F2 XgpIO[3]/EINT3/PWM_TOUT1 Y7 XgpIO[30]/XuTXD1/IrDA_TXD F3 XgpIO[31]/XuRXD1/ IrDA_RXD E1 XgpIO[4]/EINT4/PWM_TOUT2 N3 XgpIO[5]/EINT5/ PWM_TOUT3 P4 XgpIO[6]/EINT6/EXTDMA_REQ0 M2 XgpIO[7]/EINT7 EXTDMA_REQ1 L1 XgpIO[8]/EINT8/ EXTDMA_ACK0 N4 XgpIO[9]/EINT9 EXTDMA_ACK1 U4 AA3 AA2 AB4 XgPWROFFn XgREFCLKSEL[0] XgREFCLKSEL[1] XgpIO[24]/EXTDMA_REQ0/ XkpCOL1 XgpIO[25]/EXTDMA_REQ1/ XkpCOL2 XgpIO[26]/EXTDMA_ACK0/ XkpCOL3 XgpIO[27]/EXTDMA_ACK1/XkpCOL4 phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phbsu100ct8s m phob8 phis phis XgREFCLKSEL[0] I XgREFCLKSEL[1] I 1-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp I I I I L I I I/H I I I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L Hi-z or H or L H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I Hi-z - Pin Number Name Default Function XgTMODE[0] XgTMODE[1] XgTMODE[2] XgTMODE[3] XjRTCK XjTCK XjTDI XjTDO XjTMS XjTRSTn XmiADR[0] XmiADR[1] XmiADR[10] XmiADR[2] XmiADR[3] XmiADR[4] XmiADR[5] XmiADR[6] XmiADR[7] XmiADR[8] XmiADR[9] XmiCSn XmiDATA[0] XmiDATA[1] XmiDATA[2] XmiDATA[3] XmiDATA[4] XmiDATA[5] XmiDATA[6] XmiDATA[7] I/O Cell Type (24A0A) phis phis phis phis phob8 phis phisu phot8 phisu phisu phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phisu phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm Y2 W1 R1 V3 D10 B1 D2 D1 C1 C2 AA20 AB20 Y16 Y19 AC19 Y18 AC15 AA16 AB15 AA15 AC14 Y15 AB19 AC18 AA19 AC17 AB17 AC16 AA17 AB16 XgTMODE[0] XgTMODE[1] XgTMODE[2] XgTMODE[3] XjRTCK XjTCK XjTDI XjTDO XjTMS XjTRSTn XmiADR[0] XmiADR[1] XmiADR[10] XmiADR[2] XmiADR[3] XmiADR[4] XmiADR[5] XmiADR[6] XmiADR[7] XmiADR[8] XmiADR[9] XmiCSn XmiDATA[0] XmiDATA[1] XmiDATA[2] XmiDATA[3] XmiDATA[4] XmiDATA[5] XmiDATA[6] XmiDATA[7] I I I I O I I O I I I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O 1-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp H/L I I L/L I H/L I/H/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L H/L L/L Hi-z or H or L Hi-z or H or L Hi-z or H or L H or L or I Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L H L H Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre L Pin Number Name Default Function I/O Cell Type (24A0A) AB18 AB14 AA14 AA13 Y14 AC11 Y13 L23 M22 AC22 AB21 AC21 Y17 AC20 M20 M23 N21 N22 N23 P22 AB23 AC23 V23 U22 XmiIRQn XmiOEn XmiWEn XmsBS XmsPI XmsSCLKO XmsSDIO XpADDR[0] XpADDR[1] XpADDR[10] XpADDR[11] XpADDR[12] XpADDR[13] XpADDR[14] XpADDR[2] XpADDR[3] XpADDR[4] XpADDR[5] XpADDR[6] XpADDR[7] XpADDR[8] XpADDR[9] XpCASn XpCKE XmiIRQn XmiOEn XmiWEn XmsBS XmsPI XmsSCLKO XmsSDIO XpADDR[0] XpADDR[1] XpADDR[10] XpADDR[11] XpADDR[12] XpADDR[13] XpADDR[14] XpADDR[2] XpADDR[3] XpADDR[4] XpADDR[5] XpADDR[6] XpADDR[7] XpADDR[8] XpADDR[9] XpCASn XpCKE O I I O I O I/O O O O O O O O O O O O O O O O O O phot8 phisu phisu phot8 phis phot8 phbsu100ct12s m phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm 1-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp H/L H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L Hi-z or H or L Hi-z or H or L H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H H - Pin Number Name Default Function I/O Cell Type (24A0A) W22 W23 F21 E23 K22 K23 L21 L22 L20 M21 P21 R21 P23 R22 E22 T21 T22 U21 T23 T20 Y21 Y23 Y22 XpCSN[0] XpCSN[1] XpDATA[0] XpDATA[1] XpDATA[10] XpDATA[11] XpDATA[12] XpDATA[13] XpDATA[14] XpDATA[15] XpDATA[16] XpDATA[17] XpDATA[18] XpDATA[19] XpDATA[2] XpDATA[20] XpDATA[21] XpDATA[22] XpDATA[23] XpDATA[24] XpDATA[25] XpDATA[26] XpDATA[27] XpCSN[0] XpCSN[1] XpDATA[0] XpDATA[1] XpDATA[10] XpDATA[11] XpDATA[12] XpDATA[13] XpDATA[14] XpDATA[15] XpDATA[16] XpDATA[17] XpDATA[18] XpDATA[19] XpDATA[2] XpDATA[20] XpDATA[21] XpDATA[22] XpDATA[23] XpDATA[24] XpDATA[25] XpDATA[26] XpDATA[27] O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O phot12sm phot12sm phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m 1-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) Default Function I/O State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp XpDATA[28] XpDATA[29] XpDATA[3] XpDATA[30] XpDATA[31] XpDATA[4] XpDATA[5] XpDATA[6] XpDATA[7] XpDATA[8] XpDATA[9] XpDQM[0] XpDQM[1] XpDQM[2] XpDQM[3] XpRASn XpSCLK XpWEn XrADDR[0] XrADDR[1] XrADDR[10] XrADDR[11] XrADDR[12] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O I/O O O O O O O I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L H/L H/L H/L H/L H/L H or L /L H/L L/L L/L L/L L/L L/L H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L H or L or I Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L L H Pre Pre Pre Pre Pre Pin Number Name Cell Type (24A0A) phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phbsu100ct12s m phot12sm phot12sm phot12sm phot12sm phot12sm phbst12 phot12sm phot8 phot8 phot8 phot8 phot8 AA23 V21 F23 AB22 AA22 H20 G21 F22 G23 J23 K21 G22 H22 H23 J22 U23 R23 V22 D16 C14 A18 B19 D21 XpDATA[28] XpDATA[29] XpDATA[3] XpDATA[30] XpDATA[31] XpDATA[4] XpDATA[5] XpDATA[6] XpDATA[7] XpDATA[8] XpDATA[9] XpDQM[0] XpDQM[1] XpDQM[2] XpDQM[3] XpRASn XpSCLK XpWEn XrADDR[0] XrADDR[1] XrADDR[10] XrADDR[11] XrADDR[12] 1-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset I/O I/O mode Default Function I/O (Data/En/PullupEn) State@SLEEP State@STOP mode mode En(L)=>output PullupEn(L)=>PullUp XrADDR[13] XrADDR[14] XrADDR[15] XrADDR[16] XrADDR[17] XrADDR[2] XrADDR[3] XrADDR[4] XrADDR[5] XrADDR[6] XrADDR[7] XrADDR[8] XrADDR [9] XrADDR[18] XrADDR[19] XrADDR[20] XrADDR[21] XrADDR[22] XrADDR[23] XrADDR[24] XrADDR[25] XrCSn[0] O O O O O O O O O O O O O O O O O O O O O O L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L/H L/L/H L/L/H L/L/H L/L/H L/L/H L/L/H L/L/H H/L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pin Number Name Cell Type (24A0A) G20 D17 B20 A19 A20 D15 A13 D14 B14 C15 A14 D20 C20 F20 D18 A21 C21 B21 A22 E21 D23 P20 XrADDR[13] XrADDR[14] XrADDR[15] XrADDR[16] XrADDR[17] XrADDR[2] XrADDR[3] XrADDR[4] XrADDR[5] XrADDR[6] XrADDR[7] XrADDR[8] XrADDR [9] XrADDR[18] XrADDR[19] XrADDR[20] XrADDR[21] XrADDR[22] XrADDR[23] XrADDR[24] XrADDR[25] XrCSn[0] phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phot8 1-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp H/L H/L I/H/L Hi-z or H or L Hi-z or H or L H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I Hi-z or H or L Hi-z or H or L Hi-z or H or L Pre Pre Pre Pre H Pin Number Name Default Function I/O Cell Type (24A0A) C17 B17 A11 B11 C18 K20 C19 A17 B18 J20 V20 B12 U20 A12 C13 B13 A16 N20 B15 A15 R20 XrCSn[1] XrCSn[2] XrDATA[0] XrDATA[1] XrDATA[10] XrDATA[11] XrDATA[12] XrDATA[13] XrDATA[14] XrDATA[15] XrDATA[2] XrDATA[3] XrDATA[4] XrDATA[5] XrDATA[6] XrDATA[7] XrDATA[8] XrDATA[9] XrnWBE[0] XrnWBE[1] XrOEn XrCSn[1] XrCSn[2] XrDATA[0] XrDATA[1] XrDATA[10] XrDATA[11] XrDATA[12] XrDATA[13] XrDATA[14] XrDATA[15] XrDATA[2] XrDATA[3] XrDATA[4] XrDATA[5] XrDATA[6] XrDATA[7] XrDATA[8] XrDATA[9] XrnWBE[0] XrnWBE[1] XrOEn O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O phot8 phot8 phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phbsu100ct8sm phot8 phot8 phot8 I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L I/H/L H/L H/L H/L 1-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp L X I H/L I/H/L I/H/L I/H/L I/H/L I X I/H/L H/L/L I/H/L I I L L X L H or L H or L I I I I H/L I X Hi-z or H or L H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I Hi-z or H or L H or L or I H or L or I Hi-z or H or L H or L or I H H H H - Pin Number Name Default Function XrtcXTI XrtcXTO XrWAITn XrWEn XsdDAT[0] XsdDAT[1] XsdDAT[2] XsdDAT[3] XsEXTCLK XsMPLLCAP XspiCLK XspiMISO XspiMOSI XspiSSIn[0] XspiSSIn[1] XsRESETn XsRSTOUTn XsUPLLCAP XsWRESETn XsXTIN XsXTOUT XuCLK XuCTSn XudDN XudDP XuRTSn XuRXD XusDN[0] I/O Cell Type (24A0A) rtc_osc rtc_osc phis phot8 phbsu100ct12sm phbsu100ct12sm phbsu100ct12sm phbsu100ct12sm phis phob1_abb phtbsu100ct8sm phtbsu100ct8sm phtbsu100ct8sm phisu phisu phisu phot8 phob1_abb phisu phsoscm26_schmit t phsoscm26_schmit t phis phis pbusb1 pbusb1 phot8 phisu pbusb1 AA1 AB3 C16 B16 AC13 AB12 AC12 Y11 AB9 AC6 Y3 W2 V1 W3 V2 AA9 Y9 AB8 Y1 AC9 AA10 V4 T2 AB11 Y10 P1 R2 AA12 XrtcXTI XrtcXTO XrWAITn XrWEn XsdDAT[0] XsdDAT[1] XsdDAT[2] XsdDAT[3] XsEXTCLK XsMPLLCAP XspiCLK XspiMISO XspiMOSI XspiSSIn[0] XspiSSIn[1] XsRESETn XsRSTOUTn XsUPLLCAP XsWRESETn XsXTIN XsXTOUT XuCLK XuCTSn XudDN XudDP XuRTSn XuRXD XusDN[0] Ain Aout I O I/O I/O I/O I/O I Aout I/O I/O I/O I I I O Aout I I O I I I/O I/O O I I/O 1-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp X X X H/L L/L H or L or I H or L or I H or L or I Hi-z or H or L Hi-z or H or L Hi-z or H or L Hi-z or H or L H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H or L or I H L Pre L Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pre Pin Number Name Default Function I/O Cell Type (24A0A) AC10 AA11 AB10 U3 A9 C9 A8 J4 B7 K4 D7 D8 B8 B9 D12 D3 C10 B10 D13 C11 G4 XusDN[1] XusDP[0] XusDP[1] XuTXD XvDEN XvHSYNC XvVCLK XvVD[6] XvVD[7] XvVD[8] XvVD[9] XvVD[10] XvVD[11] XvVD[12] XvVD[13] XvVD[0] XvVD[14] XvVD[15] XvVD[16] XvVD[17] XvVD[1] XusDN[1] XusDP[0] XusDP[1] XuTXD XvDEN XvHSYNC XvVCLK XvVD[6] XvVD[7] XvVD[8] XvVD[9] XvVD[10] XvVD[11] XvVD[12] XvVD[13] XvVD[0] XvVD[14] XvVD[15] XvVD[16] XvVD[17] XvVD[1] I/O I/O I/O O O O O O O O O O O O O O O O O O O pbusb1 pbusb1 pbusb1 phot8 phot8 phot8 phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm phot12sm L/L H or L /L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L L/L 1-29 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments I/O state@ Reset mode I/O I/O (Data/En/PullupEn) State@SLEEP State@STOP En(L)=>output mode mode PullupEn(L)=>PullUp L/L L/L L/L L/L L/L H or L or I H or L or I H or L or I H or L or I Hi-z or H or L Pre Pre Pre Pre L Pin Number Name Default Function I/O Cell Type (24A0A) XvVD[2] C5 A6 H4 A7 D11 XvVD[3] XvVD[4] XvVD[5] XvVSYNC XvVD[2] XvVD[3] XvVD[4] XvVD[5] XvVSYNC O O O O O phot12sm phot12sm phot12sm phot12sm phot8 Notes: 1.`-` mark indicates the unchanged pin state 2. Hi-z or Pre means Hi-z or Previous value 3. P, I and O mean power, input and output respectively 4. AI/AO means analog input/output The table below shows I/O types and the descriptions. I/O Type vdd12ih vdd12ih_core vdd33oph vdd33th_abb vdd30th_rtc vdd33th_abb Vss Phis Phisu Phisd Pbusb phot8 phob8 phot12sm 1.2V Vdd for alive 1.2V Vdd for internal logic 3.3V Vdd for external logic 3.3V Vdd for analog circuit 3.3V Vdd for rtc circuit 3.3V Vdd for pll circuit Vss Input pad, LVCMOS schmitt-trigger level Input pad, schmitt-trigger level, pull-up Input pad, schmitt-trigger level, pull-down USB pad Output pad, tri-state, Io=8mA Output pad, Io=8mA Output pad, tri-state, medium slew rate, Io=12mA Descriptions 1-30 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW phbst12sm pbusb1 Rtc-osc phob1-abb phiar10_abb phia_abb phsoscm26_shmitt phbsu100ct8sm phbsu100ct12sm phbsud8sm Bi-directional pad, LVCMOS schmitt-trigger, pull-up resistor with control, tri-state, Io=12mA USB pad rtc X-tal Analog pad Analog input pad with 10-ohm resistor Analog input pad Oscillator cell with enable and feedback resistor Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri-state, Io=8mA Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri-state, Io=12mA Bi-directional pad, schmitt-trigger, pull-up resistor with, open-drain control, Io=8mA Note) phbsu100ct8sm means a bi-directional pad, but this means input pad so long as phbsu100ct8sm is used for XciCDATA[7:0] 1-31 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR 1.3 PIN DESCRIPTIONS 1.3.1 I/O Signal Descriptions 1.3.1.1 External Memory Interface * Shared Memory Bus (ROM/SRAM/NOR Flash/NAND Flash/External Bus) Signal XrADDR[25:0] XrDATA[15:0] XrCSn[2:0] I/O O IO O Description XrADDR[25:0] (Address Bus for shared memory) outputs the memory address of the corresponding bank . XrDATA[15:0] (Data Bus) inputs data during memory read and outputs data during memory write. The bus width is programmable among 8/16-bit. XrCSn[2:0] (Chip Select) are activated when the address of a memory is within the address region of each bank. The number of access cycles and the bank size can be programmed. XrWEn (Write Enable) indicates that the current bus cycle is a write cycle. XrOEn (Output Enable) indicates that the current bus cycle is a read cycle. XrWAITn requests to prolong a current bus cycle. As long as XrWAITn n is L, the current bus cycle cannot be completed. Write Byte Enable Nand Flash Command Latch Enable Nand Flash Address Latch Enable Nand Flash Page Size (0:256HWord, 1:512Byte) or Advanced Page size(0:1K Hword , 1:2K Byte) Nand Flash Bus Width (0:8-bit, 1:16-bit) Nand Flash Address Step (0:3-step, 1:4-step) or Advanced Address step(0:4-step, 1:5-step) To Support advanced 2G Nand Flash Nand Flash Ready and Busy XrWEn XrOEn XrWAITn XrnWBE[1:0] XfCLE XfALE XfNFPS XfNFBW XfNFACYC XfNFADV XfRnB[1:0] * O O I O O O I I I I I SDRAM Bank 0 Signal XpCSN[1:0] XpCASn XpRASn XpWEn XpCKE XpDQM[3:0] XpSCLK XpADDR[14:0] XpDATA[31:0] I/O O O O O O O IO O O SDRAM bank 0 Chip Select SDRAM bank 0 Column Address Strobe SDRAM bank 0 Row Address Strobe SDRAM bank 0 Write Enable SDRAM bank 0 Clock Enable SDRAM bank 0 Data Mask SDRAM bank 0 Clock SDRAM bank 0 Address bus SDRAM bank 0 Data bus Description 1-32 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW 1.3.1.2 Serial Communication * UART Signal XuCLK XuRXD0 XuCTSn0 XuTXD0 XuRTSn0 I/O I I I O O UART 0 clock signal UART 0 receives data input UART 0 clear to send input signal UART 0 transmits data output UART 0 request to send output signal Description * IIC Bus Signal X2cSDA X2cSCL I/O IO IO IIC-bus data IIC-bus clock Description * IIS Bus Signal X2sLRCK X2sDO X2sDI X2sCLK X2sCDCLK I/O IO O I IO O IIS-bus channel select clock IIS-bus serial data output IIS-bus serial data input IIS-bus serial clock CODEC system clock Description * SPI Bus Signal XspiSSIn[1:0] XspiCLK XspiMISO XspiMOSI I/O I IO IO IO SPI chip select(only for slave mode) SPI clock for channel 0 XspiMISO is the master data input line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role. For channel 0 XspiMOSI is the master data output line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role. For channel 0 Description * * AC97 Signal X97BITCLK X97SDI X97RESETn X97SYNC X97SDO I/O I I O O O Description AC-Link bit clock(12.288MHz) from AC97 Codec AC-link Serial Data input from AC97 Codec AC-link Reset to Codec AC-link Frame Synchronization (Sampling Frequency 48Khz) from AC97 Controllor AC-link Serial Data output to AC97 Codec 1-33 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR * USB Host Signal XusDN[1:0] XusDP[1:0] I/O IO IO DATA(-) from USB host DATA(+) from USB host Description * USB Device Signal XudDN XudDP I/O IO IO DATA(-) for USB peripheral device DATA(+) for USB peripheral device Description 1.3.1.3 Parallel Communication * GPIO Signal XgpIO[31:0] I/O IO General input/output ports Description * Modem Interface (8-bit Parallel) Signal XmiCSn XmiWEn XmiOEn XmiADR[10:0] XmiDATA[7:0] XmiIRQn I/O I I I I IO O Description Chip select, driven by the Modem chip Write enable, driven by the Modem chip Read enable, driven by the Modem chip Address bus, driven by the Modem chip Data bus, driven by the Modem chip Interrupt request to the Modem chip 1.3.1.4 Image/Video Processing * Camera Interface Signal XciPCLK XciVSYNC XciHREF XciCDATA[7:0] XciYDATA[7:0] XciCLK XciRSTn I/O I I I I I O O Description Pixel Clock, driven by the Camera processor Vertical Sync, driven by the Camera processor Horizontal Sync, driven by the Camera processor Pixel Data for CbCr in 16-bit mode, driven by the Camera processor Pixel Data for YCbCr in 8-bit mode or for Y in 16-bit mode, driven by the Camera processor Master Clock to the Camera processor Software Reset to the Camera processor 1-34 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW 1.3.1.5 Display Control * TFT LCD Display Interface Signal XvVD[17:0] XvVCLK XvVSYNC XvHSYNC XvDEN I/O O O O O O LCD pixel data output ports Pixel clock signal Vertical synchronous signal Horizontal synchronous signal Data enable signal Description 1.3.1.6 Input Devices * Analog-to-Digital Converter and Touch Screen Interface Signal XadcAVREF XadcAIN[7:0] I/O AI AI ADC Reference top ADC Analog Input Description 1.3.1.7 Storage Devices * Secure Digital (SD) and Memory Stick Interface Signal XsdDAT[3:0] XmsPI XmsSDIO I/O IO I IO Description SD/MMC card receive/transmit Data Input port used for insertion/extraction detect of Memory stick SD/MMC card command signal port (default). If MemoryStick card enable, Memory stick Serial data in/out port SD/MMC card Clock (default). If MemoryStick card enable, MemoryStick Clock MemoryStick Serial bus control signal XmsSCLKO XmsBS O O 1-35 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR 1.3.1.8 System Management * Reset Signal I/O I Description XsRESETn suspends any operation in progress and places S3C24A0 into a known reset state. For a reset, XsRESETn must be held to L level for at least 4 External clock after the processor power has been stabilized. System Warm Reset. Reset the whole system while preserves the SDRAM contents For external device reset control (XsRSTOUTn = XsRESETn & nWDTRST & SW_RESET & XsWRESETn) XsRESETn XsWRESETn XsRSTOUTn I O * Clock Signal XsMPLLCAP XsUPLLCAP XrtcXTI XrtcXTO XsXTIN XsXTOUT XsEXTCLK I/O AO AO AI AO I O I Loop filter capacitor for main clock. Loop filter capacitor for USB clock. 32 KHz crystal input for RTC. 32 KHz crystal output for RTC. Crystal Input for internal osc circuit. Crystal Input for internal osc circuit. External clock source. Description * JTAG Signal I/O I Description XjTRSTn (TAP Controller Reset) resets the TAP controller at start. If debugger is used, A 10K pull-up resistor has to be connected. If debugger(black ICE) is not used, TRSTn pin must be issued by a low active pulse(Typically connected to XsRESETn) XjTMS (TAP Controller Mode Select) controls the sequence of the TAP controller's states. A 10K pull-up resistor has to be connected to TMS pin. XjTCK (TAP Controller Clock) provides the clock input for the JTAG logic. A 10K pull-up resistor must be connected to TCK pin. XjRTCK (TAP Controller Returned Clock) provides the clock output for the JTAG logic. XjTDI (TAP Controller Data Input) is the serial input for test instructions and data. A 10K pull-up resistor must be connected to TDI pin. XjTDO (TAP Controller Data Output) is the serial output for test instructions and data. XjTRSTn XjTMS XjTCK XjRTCK XjTDI XjTDO I I O I O 1-36 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW * Misc Signal I/O I Clock Source Selection XgREFCLKSEL determines how the clock is made. XgREFCLKSEL[1:0] XgREFCLKSEL[0] - `0' : Main clock source is from XsXTIN, `1' : Main clock source is from XsEXTCLK XgREFCLKSEL[1] - `0' : USB clock source is from XsXTIN `1' : USB clock source is from XsEXTCLK XgTMODE[3] XgTMODE[2:1] XgTMODE[0] I I `0' : PAD JTAG(Selection of ARM core boundary scan) `1' : ARM JTAG(Selection of S3C24A0 boundary scan) These signals must be reserved `00' `0' : Normal Operation without NAND BOOT `1' : Normal Operation with NAND BOOT XgBATFLTn XgPWROFFn XgMONHCLK I O O Probe for battery state (Does not wake up at Stop and Sleep mode in case of low battery state) 1.2V core power on-off control signal HCLK clock monitoring. HCLK clock can be monitored through this pin when the ClkMonOn bit in the CLKCON register is set. Description 1.3.1.9 Power -supply Groups * VDD Signal XxVDDlogic XxVDDalive XxVDDarm XxVDDMpll XxVDDUpll XxVDDpadIO XxVDDpadSDRAM XxVDDpadFlash XxVDDpadUSB XrtcVDD XadcVDD I/O P P P P P P P P P P P Description Core logic VDD (1.2V) for internal logic S3C24A0 reset block and port status register VDD (1.2V). It should be always supplied whether in normal mode or in Stop and Sleep mode. Core logic VDD (1.2V) for CPU S3C24A0 MPLL analog and digital VDD (1.2 V). S3C24A0 UPLL analog and digital VDD (1.2V) S3C24A0 I/O port VDD (3.3V) S3C24A0 SDRAM memory IO VDD (3.3V) S3C24A0 NFLASH memory IO VDD (3.3V) S3C24A0 USB IO VDD (3.3V) RTC VDD (3.3V) (Although RTC function is not used, this pin should be connected to power) S3C24A0 ADC VDD(3.3V) 1-37 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR * VSS Signal I/O Core logic VSS for internal logic VSS for S3C24A0 reset block and port status register VSS P Core logic VSS for CPU S3C24A0 I/O port VSS XxVSSpadSDRAM XxVSSpadFlash XxVSSpadUSB XxVSSMpll XxVSSUpll XrtcVSS XadcVSS P P P P P P P S3C24A0 SDRAM memory IO VSS S3C24A0 Flash memory IO VSS S3C24A0 USB IO VSS S3C24A0 MPLL analog and digital VSS. S3C24A0 UPLL analog and digital VSS RTC VSS S3C24A0 ADC VSS Description Note: 1. I/O means input/output. 2. AI/AO means analog input/output. 3. P means power. 1-38 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW 1.4 Address MAP 1.4.1 Address Space Assignment Overview SROM_BW[9] = 0 0xFFFF_FFFF TMODE[2:0] = 000 SROM_BW[9] = 1 TMODE[2:0] = 000 TMODE[2:0] = 001 Reserved Reserved Reserved 0x5000_0000 AHB_I SFRs AHB_I SFRs AHB_I SFRs 128MB Assigned for Special Function Registers 0x4800_0000 APB SFRs 0x4400_0000 AHB_S SFRs 0x4000_0000 Reserved 0x2000_0000 SDRAM (XpCSn1) 0x1800_0000 SDRAM (XpCSn0) 0x1000_0000 Stepping stone (4KB, No CS) SROM (XrCSn2) 0x0800_0000 SROM (XrCSn1) 0x0400_0000 SROM (XrCSn0) 0x0000_0000 [Not using NAND flash for boot ROM] APB SFRs APB SFRs 64MB AHB_S SFRs AHB_S SFRs 64MB Reserved Reserved SDRAM (XpCSn1) SDRAM (XpCSn1) 128MB Assigned for SDRAM Bank0/1 Accessible Region 128MB SDRAM (XpCSn0) SDRAM (XpCSn0) Reserved Reserved SROM (XrCSn2) SROM (XrCSn1) Stepping stone (4KBytes) [Using NAND flash for boot ROM] 64MB 0x0c00_0000 Stepping stone (4KBytes) SROM (XrCSn1) SROM (XrCSn0) 64MB 64MB Assigned for SROM Bank0/1/2 Accessible Region 64MB NOTES: 1. SROM means ROM or SRAM type memory. 2. SFR means Special Function Register. Figure 1-2. Address map 1-39 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR 1.4.2 Device Specific Address Space * AHB_S (System-side AHB Bus) Devices: Base = 0x4000_0000 (just above 1GB), Size = 64MB Physical Address = Base Address + Device Offset + Register Offset Size (MB) 1 1 1 1 1 1 1 1 4 1 3 1 1 6 1 7 16 16 64 128 Group AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S AHB_S Device SystemCtrl Reserved INTC Reserved DMA 0 DMA 1 DMA 2 DMA 3 Reserved MemCtrl Reserved USB Host Modem IF0 Reserved IrDA Reserved EXT AHB Reserved APB devices AHB_I devices Note Device Offset 0x00_0_0000 0x01_0_0000 0x02_0_0000 0x03_0_0000 0x04_0_0000 0x05_0_0000 0x06_0_0000 0x07_0_0000 0x08_0_0000 0x0C_0_0000 0x0D_0_0000 0x10_0_0000 0x11_0_0000 0x12_0_0000 0x18_0_0000 0x19_0_0000 0x20_0_0000 0x30_0_0000 0x40_0_0000 0x80_0_0000 * Through AHB to APB Bridge Through AHB to AHB Bridge APB Devices: Base = 0x4000_0000 Device Offset 0x40_0_0000 0x41_0_0000 0x42_0_0000 0x43_0_0000 0x44_0_0000 0x45_0_0000 0x46_0_0000 0x47_0_0000 0x48_0_0000 0x49_0_0000 0x4A_0_0000 0x4B_0_0000 0x50_0_0000 0x51_0_0000 0x58_0_0000 0x59_0_0000 0x60_0_0000 0x61_0_0000 0x62_0_0000 0x70_0_0000 Size (MB) 1 1 1 1 1 1 1 1 1 1 1 5 1 7 1 7 1 1 14 16 Group APB APB APB APB APB APB APB APB APB APB APB APB APB APB APB APB APB APB APB APB Device PWM Timer Watch Dog Timer RTC Reserved UART SPI I2C I2S GPIO KEYPAD Interface USB Device Reserved AC97 Reserved ADC/Touch Screen Reserved SD/MMC Memory Stick Reserved Reserved Note 1-40 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW * AHB_I (the AHB Bus for the Image Subsystem) Devices: Base = 0x4000_0000 Offset (Hex) 0x80_0_0000 0x84_0_0000 0x88_0_0000 0x8C_0_0000 0x90_0_0000 0x94_0_0000 0xA0_0_0000 0xA1_0_0000 0xA2_0_0000 0xA4_0_0000 0xB0_0_0000 0xC0_0_0000 0xD0_0_0000 0xE0_0_0000 0xF0_0_0000 Size (MB) 4 4 4 4 4 12 1 1 4 10 16 16 16 16 16 Group AHB_I AHB_I AHB_I AHB_I AHB_I AHB_I AHB_I AHB_I AHB_I AHB_I AHB_I AHB_I AHB_I AHB_I AHB_I Device Camera Inteface Reserved ME MC DCT/Q Reserved Display Controller Video POST Processor Reserved VLX Reserved Reserved Reserved Reserved Reserved Note 1.4.3 Internal Registers The base of all devices internal registers = 0x4000_0000 1.4.3.1 External Memory Interface * NAND Flash Controller Register Name NFCONF NFCONT NFCMMD NFADDR NFDATA NFMECCDATA0 NFMECCDATA1 NFMECCDATA2 NFMECCDATA3 NFSECCDATA0 NFSECCDATA1 NFSTAT Offset 0x0C0_0000 0x0C0_0004 0x0C0_0008 0x0C0_000C 0x0C0_0010 0x0C0_0014 0x0C0_0018 0x0C0_001C 0x0C0_0020 0x0C0_0024 0x0C0_0028 0x0C0_002C R Acc. Unit W Read/ Write R/W Function NAND Flash Configuration NAND Flash Control NAND Flash Command NAND Flash Address NAND Flash Data NAND Flash Main area ECC Data reg.0 NAND Flash Main area ECC Data reg.1 NAND Flash Main area ECC Data reg.2 NAND Flash Main area ECC Data reg.3 NAND Flash Spare area ECC Data reg.1 NAND Flash Spare area ECC Data reg.2 NAND Flash Status 1-41 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR NFESTAT0 NFESTAT1 NFMECC0 NFMECC1 NFSECC NFSBLK NFEBLK * 0x0C0_0030 0x0C0_0034 0x0C0_0038 0x0C0_003C 0x0C0_0040 0x0C0_0044 0x0C0_0048 R/W NAND Flash ECC Status 0 for I/O[7:0] NAND Flash ECC Status 1 for I/O[15:8] NAND Flash Main Area ECC reg.0 NAND Flash Main Area ECC reg.1 NAND Flash Spare area ECC reg. NAND Flash Start Block Address NAND Flash End Block Address SROM Controller Register Name SROM_BW SROM_BC0 SROM_BC1 SROM_BC2 Offset 0x0C2_0000 0x0C2_0004 0x0C2_0008 0x0C2_000C Acc. Unit W Read/ Write R/W Function SROM Bus width & wait control SROM Bank0 Control register SROM Bank1 Control register SROM Bank2 Control register * SDRAM Controller Register Name SDRAM_BANKCFG SDRAM_BANKCON SDRAM_REFRESH Offset 0x0C4_0000 0x0C4_0004 0x0C4_0008 Acc. Unit W Read/ Write R/W SDRAM Control SDRAM Refresh Control Function SDRAM Configuration * BUS Matrix Register Name PRIORITY0 PRIORITY1 Offset 0x0CE_0000 0x0CE_0004 Acc. Unit W Read/ Write R/W Function Priority Control for SROMC/NFLASHC Priority Control for SDRAMC 1.4.3.2 General Peripherals * Interrupt Controller Register Name SRCPND INTMOD INTMSK PRIORITY Offset 0x020_0000 0x020_0004 0x020_0008 0x020_000C Acc. Unit W Read/ Write R/W Function Interrupt Request Status Interrupt Mode Control Interrupt Mask Control IRQ Priority Control 1-42 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW INTPND INTOFFSET SUBSRCPND INTSUBMSK VECINTMOD VECADDR NVECADDR VAR * 0x020_0010 0x020_0014 0x020_0018 0x020_001C 0x020_0020 0x020_0024 0x020_0028 0x020_002C R R/W R R R/W Interrupt Request Status Interrupt Request Source Offset Sub Source Pending Interrupt Sub Mask Vectored Interrupt Mode Vectored Mode Address Non-Vectored Mode Address Vector Address Register Timer with PWM (Pulse Width Modulation) Register Name TCFG0 TCFG1 TCON TCNTB0 TCMPB0 TCNTO0 TCNTB1 TCMPB1 TCNTO1 TCNTB2 TCMPB2 TCNTO2 TCNTB3 TCMPB3 TCNTO3 TCNTB4 TCNTO4 Offset 0x400_0000 0x400_0004 0x400_0008 0x400_000C 0x400_0010 0x400_0014 0x400_0018 0x400_001C 0x400_0020 0x400_0024 0x400_0028 0x400_002C 0x400_0030 0x400_0034 0x400_0038 0x400_003C 0x400_0040 R R/W R R R/W R R/W R R/W Acc. Unit W Read/ Write R/W Timer Configuration Timer Configuration Timer Control Timer Count Buffer 0 Timer Compare Buffer 0 Timer Count Observation 0 Timer Count Buffer 1 Timer Compare Buffer 1 Timer Count Observation 1 Timer Count Buffer 2 Timer Compare Buffer 2 Timer Count Observation 2 Timer Count Buffer 3 Timer Compare Buffer 3 Timer Count Observation 3 Timer Count Buffer 4 Timer Count Observation 4 Function * 16-bit Watchdog Timer. Register Name WTCON WTDAT WTCNT Offset 0x410_0000 0x410_0004 0x410_0008 Acc. Unit W Read/ Write R/W Function Watch-Dog Timer Mode Watch-Dog Timer Data Watch-Dog Timer Count 4-ch DMA controller. 1-43 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR Register Name DISRC0 DISRCC0 DIDST0 DIDSTC0 DCON0 DSTAT0 DCSRC0 DCDST0 DMASKTRIG0 DISRC1 DISRCC1 DIDST1 DIDSTC1 DCON1 DSTAT1 DCSRC1 DCDST1 DMASKTRIG1 DISRC2 DISRCC2 DIDST2 DIDSTC2 DCON2 DSTAT2 DCSRC2 DCDST2 DMASKTRIG2 DISRC3 DISRCC3 DIDST3 DIDSTC3 DCON3 DSTAT3 DCSRC3 DCDST3 DMASKTRIG3 Offset 0x040_0000 0x040_0004 0x040_0008 0x040_000C 0x040_0010 0x040_0014 0x040_0018 0x040_001C 0x040_0020 0x050_0000 0x050_0004 0x050_0008 0x050_000C 0x050_0010 0x050_0014 0x050_0018 0x050_001C 0x050_0020 0x060_0000 0x060_0004 0x060_0008 0x060_000C 0x060_0010 0x060_0014 0x060_0018 0x060_001C 0x060_0020 0x070_0000 0x070_0004 0x070_0008 0x070_000C 0x070_0010 0x070_0014 0x070_0018 0x070_001C 0x070_0020 Acc. Unit W Read/ Write R/W DMA 0 Initial Source Function DMA 0 Initial Source Control DMA 0 Initial Destination DMA 0 Initial Destination Control DMA 0 Control R DMA 0 Count DMA 0 Current Source DMA 0 Current Destination W R/W DMA 0 Mask Trigger DMA 1 Initial Source DMA 1 Initial Source Control DMA 1 Initial Destination DMA 1 Initial Destination Control DMA 1 Control R W R/W DMA 1 Count DMA 1 Current Source DMA 1 Current Destination DMA 1 Mask Trigger DMA 2 Initial Source DMA 2 Initial Source Control DMA 2 Initial Destination DMA 2 Initial Destination Control DMA 2 Control R W R/W W R/W DMA 2 Count DMA 2 Current Source DMA 2 Current Destination DMA 2 Mask Trigger DMA 3 Initial Source DMA 3 Initial Source Control DMA 3 Initial Destination DMA 3 Initial Destination Control DMA 3 Control R DMA 3 Count DMA 3 Current Source DMA 3 Current Destination R/W DMA 3 Mask Trigger 1-44 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW * RTC (Real Time Clock) Register Name RTCCON TICINT RTCALM ALMSEC ALMMIN ALMHOUR ALMDATE ALMMON ALMYEAR RTCRST BCDSEC BCDMIN BCDHOUR BCDDATE BCDDAY BCDMON BCDYEAR Offset 0x420_0040 0x420_0044 0x420_0050 0x420_0054 0x420_0058 0x420_005C 0x420_0060 0x420_0064 0x420_0068 0x420_006C 0x420_0070 0x420_0074 0x420_0078 0x420_007C 0x420_0080 0x420_0084 0x420_0088 Acc. Unit B Read/ Write R/W RTC Control Tick time count RTC Alarm Control Alarm Second Alarm Minute Alarm Hour Alarm Day Alarm Month Alarm Year RTC Round Reset BCD Second BCD Minute BCD Hour BCD Day BCD Date BCD Month BCD Year Function 1.4.3.3 Serial Communication * UART Register Name ULCON0 UCON0 UFCON0 UMCON0 UTRSTAT0 UERSTAT0 UFSTAT0 UMSTAT0 UTXH0 URXH0 UBRDIV0 ULCON1 Offset 0x440_0000 0x440_0004 0x440_0008 0x440_000C 0x440_0010 0x440_0014 0x440_0018 0x440_001C 0x440_0020 0x440_0024 0x440_0028 0x440_4000 W W B W R R/W R/W R Acc. Unit W Read/ Write R/W UART 0 Control UART 0 FIFO Control UART 0 Modem Control UART 0 Tx/Rx Status UART 0 Rx Error Status UART 0 FIFO Status UART 0 Modem Status UART 0 Transmission Hold UART 0 Receive Buffer UART 0 Baud Rate Divisor UART 1 Line Control 1-45 Function UART 0 Line Control Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR UCON1 UFCON1 UMCON1 UTRSTAT1 UERSTAT1 UFSTAT1 UMSTAT1 UTXH1 URXH1 UBRDIV1 0x440_4004 0x440_4008 0x440_400C 0x440_4010 0x440_4014 0x440_4018 0x440_401C 0x440_4020 0x440_4024 0x440_4028 W B W R R/W R UART 1 Control UART 1 FIFO Control UART 1 Modem Control UART 1 Tx/Rx Status UART 1 Rx Error Status UART 1 FIFO Status UART 1 Modem Status UART 1 Transmission Hold UART 1 Receive Buffer UART 1 Baud Rate Divisor * IIC-Bus Interface Register Name IICCON IICSTAT IICADD IICDS IICSDADLY Offset 0x460_0000 0x460_0004 0x460_0008 0x460_000C 0x460_0010 1-bit Acc. Unit W Read/ Write R/W IIC Control IIC Status IIC Address IIC Data Shift SDA Output Delay Function * IIS-Bus Interface Register Name IISCON IISMOD IISPSR IISFCON IISFIFO Offset 0x470_0000 0x470_0004 0x470_0008 0x470_000C 0x470_0010 Acc. Unit W W W W HW Read/ Write R/W IIS Control IIS Mode IIS Prescaler IIS FIFO Control IIS FIFO Entry Function * SPI Interface Register Name SPCON0 SPSTA0 SPPIN0 SPPRE0 SPTDAT0 SPRDAT0 Offset 0x450_0000 0x450_0004 0x450_0008 0x450_000C 0x450_0010 0x450_0014 R Acc. Unit W Read/ Write R/W R R/W Function SPI Channel 0 Control SPI Channel 0 Status SPI Channel 0 Pin Control SPI Channel 0 Baud Rate Prescaler SPI Channel 0 Tx Data SPI Channel 0 Rx Data 1-46 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW SPCON1 SPSTA1 SPPIN1 SPPRE1 SPTDAT1 SPRDAT1 0x450_0020 0x450_0024 0x450_0028 0x450_002C 0x450_0030 0x450_0034 R/W R R/W SPI Channel 1 Control SPI Channel 1 Status SPI Channel 1 Pin Control SPI Channel 1 Baud Rate Prescaler SPI Channel 1 Tx Data R SPI Channel 1 Rx Data * AC97 Audio-CODEC Interface Register Name AC_GLBCTRL AC_GLBSTAT AC_CODEC_CMD AC_CODEC_STAT AC_PCM_ADDR AC_MICADDR AC_PCMDATA AC_MICDATA Offset 0x500_0000 0x500_0004 0x500_0008 0x500_000C 0x500_0010 0x500_0014 0x500_0018 0x500_001C Acc. Unit W Read/ Write R/W R R/W R R R R/W R/W Function AC97 Global Control AC97 Global Status AC97 Codec Command AC97 Codec Status AC97 PCM Out/In Channel FIFO Address AC97 Mic In Channel FIFO Address AC97 PCM Out/In Channel FIFO Data AC97 Mic In Channel FIFO Data * USB Host Register Name HcRevision HcControl HcCommonStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCuttentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining Offset 0x100_0000 0x100_0004 0x100_0008 0x100_000C 0x100_0010 0x100_0014 0x100_0018 0x100_001C 0x100_0020 0x100_0024 0x100_0028 0x100_002C 0x100_0030 0x100_0034 0x100_0038 Frame Counter Group Memory Pointer Group Acc. Unit W Read/ Write Function Control and Status Group 1-47 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 * 0x100_003C 0x100_0040 0x100_0044 0x100_0048 0x100_004C 0x100_0050 0x100_0054 0x100_0058 Root Hub Group USB Device Register Name FUNC_ADDR_REG PWR_REG EP_INT_REG USB_INT_REG EP_INT_EN_REG USB_INT_EN_REG FRAME_NUM1_REG INDEX_REG EP0_CSR IN_CSR1_REG IN_CSR2_REG MAXP_REG OUT_CSR1_REG OUT_CSR2_REG OUT_FIFO_CNT1_REG OUT_FIFO_CNT2_REG EP0_FIFO EP1_FIFO EP2_FIFO EP3_FIFO EP4_FIFO EP1_DMA_CON EP1_DMA_UNIT EP1_DMA_FIFO EP1_DMA_TTC_L Offset 0x4A0_0140 0x4A0_0144 0x4A0_0148 0x4A0_0158 0x4A0_015C 0x4A0_016C 0x4A0_0170 0x4A0_0178 0x4A0_0184 0x4A0_0184 0x4A0_0188 0x4A0_0180 0x4A0_0190 0x4A0_0194 0x4A0_0198 0x4A0_019C 0x4A0_01C0 0x4A0_01C4 0x4A0_01C8 0x4A0_01CC 0x4A0_01D0 0x4A0_0200 0x4A0_0204 0x4A0_0208 0x4A0_020C R/W R R R/W Acc. Unit B Read/ Write R/W Function Function Address Power Management EP Interrupt Pending and Clear USB Interrupt Pending and Clear Interrupt Enable Interrupt Enbale Frame Number Lower Byte Register Index Endpoint 0 Status In Endpoint Control Status In Endpoint Control Status Endpoint Max Packet Out Endpoint Control Status Out Endpoint Control Status Endpoint Out Write Count Endpoint Out Write Count Endpoint 0 FIFO Endpoint 1 FIFO Endpoint 2 FIFO Endpoint 3 FIFO Endpoint 4 FIFO EP1 DMA Interface Control EP1 DMA Tx Unit Counter EP1 DMA Tx FIFO Counter EP1 DMA Total Tx Counter 1-48 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW EP1_DMA_TTC_M EP1_DMA_TTC_H EP2_DMA_CON EP2_DMA_UNIT EP2_DMA_FIFO EP2_DMA_TTC_L EP2_DMA_TTC_M EP2_DMA_TTC_H EP3_DMA_CON EP3_DMA_UNIT EP3_DMA_FIFO EP3_DMA_TTC_L EP3_DMA_TTC_M EP3_DMA_TTC_H EP4_DMA_CON EP4_DMA_UNIT EP4_DMA_FIFO EP4_DMA_TTC_L EP4_DMA_TTC_M EP4_DMA_TTC_H * 0x4A0_0210 0x4A0_0214 0x4A0_0218 0x4A0_021C 0x4A0_0220 0x4A0_0224 0x4A0_0228 0x4A0_022C 0x4A0_0240 0x4A0_0244 0x4A0_0248 0x4A0_024C 0x4A0_0250 0x4A0_0254 0x4A0_0258 0x4A0_025C 0x4A0_0260 0x4A0_0264 0x4A0_0268 0x4A0_026C B R/W EP1 DMA Total Tx Counter EP1 DMA Total Tx Counter EP2 DMA Interface Control EP2 DMA Tx Unit Counter EP2 DMA Tx FIFO Counter EP2 DMA Total Tx Counter EP2 DMA Total Tx Counter EP2 DMA Total Tx Counter EP3 DMA Interface Control EP3 DMA Tx Unit Counter EP3 DMA Tx FIFO Counter EP3 DMA Total Tx Counter EP3 DMA Total Tx Counter EP3 DMA Total Tx Counter EP4 DMA Interface Control EP4 DMA Tx Unit Counter EP4 DMA Tx FIFO Counter EP4 DMA Total Tx Counter EP4 DMA Total Tx Counter EP4 DMA Total Tx Counter IrDA Register Name IrDA _CNT IrDA_MDR IrDA_CNF IrDA _IER IrDA _IIR IrDA _LSR IrDA _FCR IrDA _PLR IrDA_RBR IrDA_TXNO IrDA_RXNO IrDA _TXFLL Offset 0x180_0000 0x180_0004 0x180_0008 0x180_000C 0x180_0010 0x180_0014 0x180_0018 0x180_001C 0x180_0020 0x180_0024 0x180_0028 0x180_002C R/W R R/W R Acc. Unit W Read/ Write R/W IrDA Control r IrDA Mode Definition IrDA Interrupt / DMA Configuration IrDA Interrupt Enable IrDA Interrupt Identification IrDA Line Status IrDA FIFO Control IrDA Preamble Length IrDA Receiver & Transmitter Buffer The total number of data bytes remained in Tx FIFO The total number of data bytes remained in Rx FIFO IrDA Transmit Frame-Length Register Low Function 1-49 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR IrDA _TXFLH IrDA _RXFLL IrDA _RXFLH 0x180_0030 0x180_0034 0x180_0038 IrDA Transmit Frame-Length Register High IrDA Receive Frame-Length Register Low IrDA Receive Frame-Length Register High 1.4.3.4 Parallel Communication * Modem Interface Register Name INT2AP INT2MDM Offset 0x118_0000 0x118_0004 Acc. Unit W Read/ Write R/W Function Interrupt Request to AP Register Interrupt request to MODEM Register * GPIO Register Name GPCON_U GPCON_M GPCON_L GPDAT GPPU EXTINTC0 EXTINTC1 EXTINTC2 EINTFLT0 EINTFLT1 EINTMASK EINTPEND PERIPU ALIVECON GPDAT_SLEEP GPOEN_SLEEP GPPU_SLEEP PERIDAT_SLEEP0 PERIDAT_SLEEP1 PERIOEN_SLEEP0 PERIOEN_SLEEP1 Offset 0x480_0000 0x480_0004 0x480_0008 0x480_000C 0x480_0010 0x480_0018 0x480_001C 0x480_0020 0x480_0024 0x480_0028 0x480_0034 0x480_0038 0x480_0040 0x480_0044 0x480_0048 0x480_004C 0x480_0050 0x480_0054 0x480_0058 0x480_005C 0x480_0060 Acc. Unit W Read/ Write R/W Function GPIO Ports Configuration Register GPIO Ports Configuration Register GPIO Ports Configuration Register GPIO Ports Data Register GPIO Ports Pull-up Control Register External Interrupt Control Register 0 External Interrupt Control Register 1 External Interrupt Control Register 2 External Interrupt Filter Control Register 0 External Interrupt Filter Control Register 1 External interupt mask Register External Interupt Pending Register Peri. Ports Pull-up Control Register Alive Control Register GPIO Output Data for Sleep Mode GPIO Output Enable Control for Sleep Mode GPIO Pull-up Control Register for Sleep Mode Peri. Ports Output Data Control Register 0 for sleep mode Peri. Ports Output Data Control Register 1 for sleep mode Peri. Ports Output Control Register 0 for sleep mode Peri. Ports Output Control Register 1 for sleep mode 1-50 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW PERIPU_SLEEP RSTCNT GPRAM0~15 0x480_0064 0x480_0068 0x480_0080 ~0x480_00BC Peri. Ports Pull-up Control Register for slee mode Reset Count Compare Register General purpose RAM array 1.4.3.5 Image/Video Processing * Camera Interface Register Name CISRCFMT CIWDOFST CIGCTRL CICOYSA1 CICOYSA2 CICOYSA3 CICOYSA4 CICOCBSA1 CICOCBSA2 CICOCBSA3 CICOCBSA4 CICOCRSA1 CICOCRSA2 CICOCRSA3 CICOCRSA4 CICOTRGFMT CICOCTRL CICOSCPRERATIO CICOSCPREDST CICOSCCTRL CICOTAREA CICOSTATUS CIPRCLRSA1 Offset 0x800_0000 0x800_0004 0x800_0008 0x800_0018 0x800_001C 0x800_0020 0x800_0024 0x800_0028 0x800_002C 0x800_0030 0x800_0034 0x800_0038 0x800_003C 0x800_0040 0x800_0044 0x800_0048 0x800_004C 0x800_0050 0x800_0054 0x800_0058 0x800_005C 0x800_0064 0x800_006C 0x800_0070 0x800_0074 R R/W Acc. Unit W Read/ Write R/W Function Input Source Format Window offset register Global control register Y 1 frame start address for codec DMA Y 2 frame start address for codec DMA Y 3 frame start address for codec DMA Y 4 frame start address for codec DMA Cb 1 frame start address for codec DMA Cb 2 frame start address for codec DMA Cb 3 frame start address for codec DMA Cb 4 frame start address for codec DMA Cr 1 frame start address for codec DMA Cr 2 frame start address for codec DMA Cr 3 frame start address for codec DMA Cr 4 frame start address for codec DMA Target image format of codec DMA Codec DMA control related Codec pre-scaler ratio control Codec pre-scaler destination format Codec main-scaler control Codec pre-scaler destination format Codec path status RGB 1 frame start address for preview DMA RGB 2 frame start address for preview DMA RGB 3 frame start address for preview DMA rd nd st th rd nd st th rd nd st th rd nd st CIPRCLRSA2 CIPRCLRSA3 1-51 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR CIPRCLRSA4 CIPRTRGFMT CIPRCTRL CIPRSCPRERATIO CIPRSCPREDST CIPRSCCTRL CIPRTAREA CIPRSTATUS CIIMGCPT 0x800_0078 0x800_007C 0x800_0080 0x800_0084 0x800_0088 0x800_008C 0x800_0090 0x800_0098 0x800_00A0 R R/W RGB 4 frame start address for preview DMA Target image format of preview DMA Preview DMA control related Preview pre-scaler ratio control Preview pre-scaler destination format Preview main-scaler control Preview pre-scaler destination format Preview path status Image capture enable command th * Video POST Register Name MODE PreScale_Ratio PreScaleImgSize SRCImgSize MainScale_H_Ratio MainScale_V_Ratio DSTImgSize PreScale_SHFactor ADDRStart_Y ADDRStart_Cb ADDRStart_Cr ADDRStart_RGB ADDREnd_Y ADDREnd_Cb ADDREnd_Cr ADDREnd_RGB Offset_Y Offset_Cb Offset_Cr Offset_RGB Offset 0xA10_0000 0xA10_0004 0xA10_0008 0xA10_000C 0xA10_0010 0xA10_0014 0xA10_0018 0xA10_001C 0xA10_0020 0xA10_0024 0xA10_0028 0xA10_002C 0xA10_0030 0xA10_0034 0xA10_0038 0xA10_003C 0xA10_0040 0xA10_0044 0xA10_0048 0xA10_004C Acc. Unit W Read/ Write R/W Mode Register [9:0] Pre-Scale ratio for vertical and horizontal. Pre-Scaled image size Source image size Main scale ratio along to horizontal direction Main scale ratio along to vertical direction Destination image size Pre-scale shift factor DMA Start address for Y or RGB component DMA Start address for Cb component DMA Start address for Cr component DMA Start address for RGB component DMA End address for Y or RGB component DMA End address for Cb component DMA End address for Cr component DMA End address for RGB component Offset of Y component for fetching source image Offset of Cb component for fetching source image Offset of Cr component for fetching source image Offset of RGB component for restoring destination image Function 1-52 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW ME Register Name ME_CFSA ME_PFSA ME_MVSA ME_CMND ME_STAT_SWR ME_CNFG ME_IMGFMT * Offset 0x880_0000 0x880_0004 0x880_0008 0x880_000C 0x880_0010 0x880_0014 0x880_0018 Acc. Unit Read/ Write Function Current Frame Start Address Register Previous Frame Start Address Register Motion Vector Start Address Register Command Register Status & S/W Reset Register Configuration Register Image Format Register W R/W MC Register Name MC_PFYSA_ENC MC_CFYSA_ENC Offset 0x8C0_0000 0x8C0_0004 Acc. Unit W Read/ Write R/W Function Previous Frame Y Start Address Register for the Encoder MCed Frame Y Start Address Register for the Encoder Previous Frame Y Start Address Register for the Decoder MCed Frame Y Start Address Register for the Decoder Previous Frame Cb Start Address Register for the Encoder Previous Frame Cr Start Address Register for the Encoder MCed Frame Cb Start Address Register for the Encoder MCed Frame Cr Start Address Register for the Encoder Previous Frame Cb Start Address Register for the Decoder Previous Frame Cr Start Address Register for the Decoder MCed Frame Cb Start Address Register for the Decoder MCed Frame Cr Start Address Register for the Decoder Motion Vector Start Address Register for the Encoder MC_PFYSA_DEC MC_CFYSA_DEC MC_PFCbSA_ENC MC_PFCrSA_ENC MC_CFCbSA_ENC MC_CFCrSA_ENC MC_PFCbSA_DEC MC_PFCrSA_DEC MC_CFCbSA_DEC MC_CFCrSA_DEC MC_MVSA_ENC 0x8C0_0008 0x8C0_000C 0x8C0_0010 0x8C0_0014 0x8C0_0018 0x8C0_001C 0x8C0_0020 0x8C0_0024 0x8C0_0028 0x8C0_002C 0x8C0_0030 1-53 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR MC_MVSA_DEC MC_CMND MC_STAT_SWR MC_CNFG MC_IMGFMT * 0x8C0_0034 0x8C0_0038 0x8C0_003C 0x8C0_0040 0x8C0_0044 Motion Vector Start Address Register for the Decoder Command Register Status & S/W Reset Register Configuration Register Image Format Register DCTQ Register Name SAYCF SACBCF SACRCF SAYRF SACBRF SACRRF SAYDQF SACBDQF SACRDQF SAQP IMGSIZE SHQ DCTQCTRL Offset 0x900_0000 0x900_0004 0x900_0008 0x900_000C 0x900_0010 0x900_0014 0x900_0018 0x900_001C 0x900_0020 0x900_0024 0x900_0028 0x900_002C 0x900_0034 Acc. Unit W Read/ Write R/W Function Current frame luminance start address Current frame Cb start address Current frame Cr start address Reconstruction address frame luminance start Reconstruction frame Cb start address Reconstruction frame Cr start address DCTQed frame luminance start address DCTQed frame Cb start address DCTQed frame Cr start address Qp start address Image horizontal and vertical pixel number Short header quantization mode Control register * VLX Register Name VLX_COMMON1 VLX_FRAMESTARTY VLX_FRAMESTARTCB VLX_FRAMESTARTCR VLC_CON1 VLC_CON2 Offset 0x940_0000 0x940_0004 0x940_0008 0x940_000C 0x940_0010 0x940_0014 Acc. Unit W Read/ Write R/W Function VLX common control register1 Y coeff. start address Cb coeff. frame start address Cr coeff. frame start address Control register in VLC mode Reserved 1-54 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW VLC_CON3 VLC_CON4 VLD_CON1 VLD_CON2 VLD_CON3 VLX_OUT1 VLX_OUT2 0x940_0018 0x940_001C 0x940_0020 0x940_0024 0x940_0028 0x940_002C 0x940_0030 R VLC result external address Reserved Control register in VLD mode VLCed bit stream start address Reserved VLX output information register 1 VLX output information register 2 1.4.3.6 Display Control * TFT LCD Controller Register LCDCON1 LCDCON2 LCDTCON1 LCDTCON2 LCDTCON3 LCDOSD1 LCDOSD2 LCDOSD3 LCDSADDRB1 LCDSADDRB2 LCDSADDRF1 LCDSADDRF2 LCDEADDRB1 LCDEADDRB2 LCDEADDRF1 LCDEADDRF2 LCDVSCRB1 LCDVSCRB2 LCDVSCRF1 LCDVSCRF2 LCDINTCON LCDKEYCON Offset 0xA00_0000 0xA00_0004 0xA00_0008 0xA00_000C 0xA00_0010 0xA00_0014 0xA00_0018 0xA00_001C 0xA00_0020 0xA00_0024 0xA00_0028 0xA00_002C 0xA00_0030 0xA00_0034 0xA00_0038 0xA00_003C 0xA00_0040 0xA00_0044 0xA00_0048 0xA00_004C 0xA00_0050 0xA00_0054 Acc. Unit W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LCD Control 1 LCD Control 2 LCD Time Control 1 LCD Time Control 2 LCD Time Control 3 LCD OSD Control Register Foreground image(OSD Image) Left top position set Foreground image(OSD Image) Right Bottom position set Frame Buffer Start Address 1 ( Background buffer 1) Frame Buffer Start Address 2 ( Background buffer 2) Frame Buffer Start Address 1 ( foreground buffer 1) Frame Buffer Start Address 2 ( foreground buffer 2) Frame Buffer End Address 1 ( Background buffer 1) Frame Buffer End Address 2 ( Background buffer 2) Frame Buffer End Address 1 ( foreground buffer 1) Frame Buffer End Address 2 ( foreground buffer 2) Virtual Screen Offsize and Pagewidth ( Background buffer 1) Virtual Screen Offsize and Pagewidth ( Background buffer 2) Virtual Screen Offsize and Pagewidth ( Foreground buffer 1) Virtual Screen Offsize and Pagewidth ( Foreground buffer 2) LCD Interrupt Control COLOR KEY Control 1 1-55 Function Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR LCDKEYVAL LCDBGCON LCDFGCON LCDDITHCON 1.4.3.7 Input Devices * 0xA00_0058 0xA00_005C 0xA00_0060 0xA00_0064 R/W R/W R/W R/W COLOR KEY Control 2 Back-ground color Control Fore-ground color Control LCD Dithering Control for Active Matrix Keypad Interface Register Name KEYDAT KEYINTC KEYFLT0 KEYFLT1 KEYMAN Offset 0x490_0000 0x490_0004 0x490_0008 0x490_000C 0x490_0010 Acc. Unit W Read/ Write R/W Function The data register for KEYPAD input KEYPAD input ports Interrupt Control KEY PAD Input Filter Control KEY PAD Input Filter Control KEYPAD manual scan control * Analog-to-Digital Converter and Touch Screen Interface Register Name ADCCON ADCTSC ADCDLY ADCDAX ADCDAY Offset 0x580_0000 0x580_0004 0x580_0008 0x580_000C 0x580_0010 R Acc. Unit W Read/ Write R/W ADC Control ADC Touch Screen Control ADC Start or Interval Delay ADC Conversion Data Register X ADC Conversion Data Register Y Function 1.4.3.8 Storage Devices * SD and SDIO / MMC Register Name SDICON SDIPRE SDICARG SDICCON SDICSTA SDIRSP0 SDIRSP1 SDIRSP2 SDIRSP3 SDIDTIMER Offset 0x600_0000 0x600_0004 0x600_0008 0x600_000C 0x600_0010 0x600_0014 0x600_0018 0x600_001C 0x600_0020 0x600_0024 R/W R/(C) R Acc. Unit W Read/ Write R/W SDI Control SDI Buad Rate Prescaler SDI Command Argument SDI Command Control SDI Command Status SDI Response SDI Response SDI Response SDI Response SDI Data / Busy Timer Function 1-56 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR PRELIMINARY PRODUCT OVERVIEW SDIBSIZE SDIDCON SDIDCNT SDIDSTA SDIFSTA SDIIMSK SDIDAT0 SDIDAT1 SDIDAT2 SDIDAT3 * 0x600_0028 0x600_002C 0x600_0030 0x600_0034 0x600_0038 0x600_003C 0x600_0040 0x600_0044 0x600_0048 0x600_004C B,HW,W W W R/W R R/(C) R/(C) R/W SDI Block Size SDI Data control SDI Data Remain Counter SDI Data Status SDI FIFO Status SDI Interrupt Mask SDI Data0 SDI Data1 SDI Data2 SDI Data3 Memory Stick Register Name MSPRE MSFINTCON TP_CMD CTRL_STA DAT_FIFO INTCTRL_STA INS_CON ACMD_CON ATP_CMD Offset 0x610_0000 0x610_0004 0x610_8000 0x610_8004 0x610_8008 0x610_800C 0x610_8010 0x610_8014 0x610_8018 Acc. Unit W Read/ Write R/W Prescaler Control FIFO Interrupt Control Transfer Protocol Command Command and Status Data FIFO Interrupt Control and Status INS Port Control Auto Command and Polarity Control Auto Transfer Protocol Command Function 1.4.3.8 System Management * PLL Clock Control and Power Management Register Name LOCKTIME OSCWSET MPLLCON UPLLCON CLKCON CLKSRC CLKDIVN PWRMAN SOFTRESET Offset 0x000_0000 0x000_0004 0x000_0010 0x000_0014 0x000_0020 0x000_0024 0x000_0028 0x000_0030 0x000_0038 Acc. Unit W Read/ Write R/W Function PLL Lock Time Counter OSC settle-down wait time setting MPLL Configuration UPLL Configuration Clock Generator Control Slow Clock Control Clock divider Control Power Management Software Reset 1-57 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PRELIMINARY PRODUCT OVERVIEW S3C24A0 RISC MICROPROCESSOR IMPORTANT NOTES ABOUT S3C24A0 SPECIAL REGISTERS 1. The special registers have to be accessed by the recommended access unit. 2. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32bit) at little/big endian. 3. It is very important that the ADC registers, RTC registers and UART registers be read/written by the specified access unit and the specified address. Moreover, one must carefully consider which endian mode is used. 4. W : 32-bit register, which must be accessed by LDR/STR or int type pointer(int *). HW : 16-bit register, which must be accessed by LDRH/STRH or short int type pointer(short int *). B : 8-bit register, which must be accessed by LDRB/STRB or char type pointer(char int *). . 1-58 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SROM CONTROLLER SROM CONTROLLER(Preliminary) OVERVIEW S3C24A0 support external 16-bit bus for NAND Flash/ NOR Flash/ PROM/ SRAM external memory. It's not shared with SDRAM bus and support up to 3 Bank for one controller. From now on, we call this controller as SROM Controller. Below figure show the Address Map configuration of S3C24A0 SROM Controller. S3C24A0 SROM Controller has 3 kinds of configuration. If user want to use NAND boot loader, it'll be selected the third configuration which stepping stone (SRAM 4KB) is on the 0x00000000. And If user want to use ROM type boot, it'll be selected the first or second configuration by selecting SFR (Special Function Register) of SROM Controller. In this case user can use NAND Flash Memory for other usage. At the first configuration, Stepping Stone is used just for buffer of any master. SROM_BW[9] = 0 0xFFFF_FFFF TMODE[2:0] = 000 Reserved 0x5000_0000 SROM_BW[9] = 1 TMODE[2:0] = 000 Reserved TMODE[2:0] = 001 Reserved AHB/APB SFRs AHB/APB SFRs AHB/APB SFRs 256MB Assigned for Special Function Registers 0x4000_0000 Reserved 0x2000_0000 SDRAM (BANK0/1) 0x1000_0000 SRAM Buffer (4KB, No CS) SROM (BANK2, XrCSn2) 0x0800_0000 SROM (BANK1, XrCSn1) 0x0400_0000 SROM (BANK0, XrCSn0) 0x0000_0000 [Not using NAND flash for boot ROM] Reserved Reserved SDRAM (BANK0/1) SDRAM (BANK0/1) 256MB Assigned for SDRAM Bank0/1 Accessible Region Reserved Reserved SROM (BANK2, XrCSn2) SROM (BANK1, XrCSn1) Stepping stone (4KBytes) [Using NAND flash for boot ROM] 64MB 0x0c00_0000 Stepping stone (4KBytes) SROM (BANK1, XrCSn1) SROM (BANK0, XrCSn0) 64MB 64MB Assigned for SROM Bank0/1/2 Accessible Region 64MB NOTES: 1. SROM means ROM or SRAM type memory. 2. SFR means Special Function Register. Figure 2-1. SROM Controller Address Mapping 2-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SROM CONTROLLER S3C24A0 RISC MICROPROCESSOR FEATURE Supports SRAM, various ROMs and NOR flash memory Supports only 8 or 16-bit data bus Address space : Up to 64MB per Bank Supports 3 banks (XrCSn[2:0]) Boot by NAND Flash Memory : XrCSn0's owner is not SROM Controller but NAND Controller. Boot by other Memory (Nor Flash or ROM): XrCSn2's owner is either SROM Controller or NAND Controller (User can choose it by setting SFR). Fixed memory bank start address External wait to extend the bus cycle Support byte, half-word and word access for external memory - BLOCK DIAGRAM AHB I/F for SROM SFR SROM DECODER SFR SROM I/F SINGAL GENERATO N CONTROL & STATE MACHINE SROM MEM I/F AHB I/F for SROM MEM Figure 2-2 SROM Controller Block Diagram 2-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SROM CONTROLLER FUNCTION DESCRIPTION SROM Controller support SROM interface for Bank0 to Bank2. In case of NAND boot, SROM controller can't control Bank0 because of its mastership is on NAND Flash Controller. In case of ROM boot, as it mentioned before, it is possible that Bank2's master is NAND Flash Controller by setting of users. Address-bus : 26-bit Data-bus : 8/16 SRAM/ROM/ NOR FLASH/ NAND FLASH SRAM/ROM/ NOR FLASH SRAM/ROM/ NOR FLASH /NAND FLASH SROM CONTROLLER MEMORY BUS #1 BANK0 BANK1 BANK2 Figure 2-3 Memory Interface Block Diagram 2-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SROM CONTROLLER S3C24A0 RISC MICROPROCESSOR XrWAITn PIN OPERATION If the WAIT corresponding to each memory bank is enabled, the XrOEn duration should be prolonged by the external XrWAITn pin while the memory bank is active. XrWAITn is checked from Tacc-1. The XrOEn will be deasserted at the next clock after sampling XrWAITn is high. The XrWEn signal have the same relation with XrOEn. HCLK XrADDR [25:0] XrCSn [2:0] XrOEn Tcos Sampling XrWAITn XrWAITn XrDATA [15:0] (R) Tacs Tacc=4 Delayed Figure 2-4 XrWAITn pin operation 2-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SROM CONTROLLER PROGRAMMABLE ACCESS CYCLE WRITE TO READ WAVEFORM HCLK XrADDR [25:0] XrCSn [2:0] XrOEn Tcoh Tacc XrWEn XrnWBE [1:0] XrDATA [15:0] (R) XrDATA [15:0] (W) Tacs = 1 cycle Tcos = 1 cycle Tacc = 2 cycles Tacs Tcos Tcah Tcoh = 1 cycle Tcah = 2 cycles Figure 2-4 Programmable access cycle 2-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SROM CONTROLLER S3C24A0 RISC MICROPROCESSOR SPECIAL FUNCTION REGISTERS SROM BUS WIDTH & WAIT CONTRL REGISTER(SROM_BW) Register Address SROM_BW 0x40C20000 R/W R/W Description SROM Bus width & wait control Reset Value 0x000x SROM_BW Reserved BankNum Bit [15:9] [9] Description Reserved 0 = XrCSn2's owner is SROM Controller (In this case Stepping Stone is just used as 4KB SRAM buffer) 1 = XrCSn2's owner is NAND Flash Controller This bit determines SRAM for using UB/LB for bank2 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0] Initial State 0x00 0x00 ST2 [8] 0 WS2 DW2 ST1 [7] [6] [5] This bit determines WAIT status for bank2 0 = WAIT disable 1 : WAIT enable Indicates data bus width for bank2 0 = 8-bit 1 : 16-bit This bit determines SRAM for using UB/LB for bank1 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0] 0 0 0 WS1 DW1 ST0 [4] [3] This bit determines WAIT status for bank1 0 = WAIT disable 1 : WAIT enable Indicates data bus width for bank1 0 = 8-bit 1 : 16-bit This bit determines SRAM for using UB/LB for bank0 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0] 0 0 [2] 0 WS0 DW0 [1] [0] This bit determines WAIT status for bank0 0 = WAIT disable 1 : WAIT enable Indicates data bus width for bank0 (read only) 0 : 8-bit 1 : 16-bit 0 H/W Set * DW0 is read only. The value is written by external configuration pin(XfNFBW) 2-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SROM CONTROLLER SROM BANK CONTROL REGISTER (SROM_BC : XrCSn0 ~ XrCSn2) Register SROM_BC0 SROM_BC1 SROM_BC2 Address 0x40C20004 0x40C20008 0x40C2000C R/W R/W R/W R/W Description SROM Bank0 control register SROM Bank1 control register SROM Bank2 control register Reset Value 0x0700 0x0700 0x0700 SROM_BCn Tacs Bit [15:14] Tcos [13:12] Reserved Tacc [11] [10:8] Tcoh [7:6] Tcah [5:4] Reserved [3:0] Description Adress set-up before XrCSn[2:0] 00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks Chip selection set-up XrOEn 00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks Reserved Access cycle 000 = 2 clock 001 = 3 clocks 010 = 4 clocks 011 = 10 clocks 100 = 12 clocks 101 = 14 clocks 110 = 16 clock 111 = 20 clocks Chip selection hold on XrOEn 00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks Address holding time after XrCSn[2:0] 00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks Reserved Initial State 00 00 0 111 00 00 0000 2-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDRAM CONTROLLER 3 * SDRAM CONTROLLER (Preliminary) OVERVIEW The S3C24A0 SDRAM Controller has the following features: SDRAM - - - - - - - - - - Supports 16-bit or 32-bit data bus Supports 2 banks: XpCSN[1:0] 16-bit Refresh Timer Self Refresh Mode Programmable CAS Latency Provide Write buffer (4word size x2) Provide long burst(INCR8,16 & WRAP8,16) transfer Provide Power Down Mode Support mobile SDRAM Support extended MRS set (EMRS) - DS , TSCR, PASR 3-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SDRAM CONTROLLER S3C24A0 RISC MICROPROCESSOR SELECTION OF SDRAM We recommanded select one of the SDRAM configurations in Table 3-1. And, each two banks should have same bus width. Table 3-1. Supported SDRAM configuration Total Size 4MB 8MB Bus Width x32 Base Component 16Mb 64Mb 16Mb 16MB 128Mb 64Mb 32MB 256Mb 128Mb 64Mb 64MB 256Mb 128Mb 512Mb 128MB 256Mb 512Mb 2MB 4MB 8MB 16MB x16 16Mb 16Mb 64Mb 128Mb 64Mb 32MB 256Mb 128Mb 64MB 256Mb 512Mb Memory Configuration (512Kbit x 16bit x 2Bank) x 2ea (512K x 32 x 4) x 1 (1M x 8 x 2) x 4 (1M x 32 x 4) x 1 (1M x 16 x 4) x 2 (2M x 32 x 4) x 1 (2M x 16 x 4) x 2 (2M x 8 x 4) x 4 (4M x 16 x 4) x 2 (4M x 8 x 4) x 4 (4M x 32 x 4) x 1 (8M x 8 x 4) x 4 (8M x 16 x 4) x 2 (512K x 16 x 2) x 1 (1M x 8 x 2) x 2 (1M x 16 x 4) x 1 (2M x 16 x 4) x 1 (2M x 8 x 4) x 2 (4M x 16 x 4) x 1 (4M x 8 x 4) x 2 (8M x 8 x 4) x 2 (8M x 16 x 4) x 1 Bank Address A13 A[14:13] A13 A[14:13] A[14:13] A[14:13] A[14:13] A[14:13] A[14:13] A[14:13] A[14:13] A[14:13] A[14:13] A13 A13 A[14:13] A[14:13] A[14:13] A[14:13] A[14:13] A[14:13] A[14:13] SELF REFRESH The S3C24A0 provides the auto refresh and self refresh command to sustain the contents of SDRAM. The auto refresh is issued to SDRAM periodically when refresh timer is expired. The self refresh is entered and exited by request of on-chip power manager. 3-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDRAM CONTROLLER SDRAM INITIALIZATION SEQUENCE On power-on reset, software must initialize the memory controller and each of the SDRAM connected to the controller. Refer to the SDRAM data sheet for the start up procedure, and examples sequence is given below: 1. 2. 3. 4. 5. 6. 7. 8. 9. Wait 200us to allow SDRAM power and clock stabilize. Program the INIT[1:0] to `01b'. This automatically issues a PALL(pre-charge all) cammand to the SDRAM. Write `0x20' into the refresh timer register. This provides a refresh cycle every 32-clock cycles. Wait for a time period equivalent to 128-clock cycles (4 refresh cycles). Program the normal operational value into the refresh timer.. Program the configuration registers to their normal operation values. Program the INIT[1:0] to `10b'. This automatically issues a MRS command to the SDRAM. Mobile only Program the INIT[1:0] to `11b'. This automatically issues a EMRS command to the SDRAM. Program the INIT[1:0] to `00b'. The controller enters the normal mode. 10. The SDRAM is now ready for normal operation. Note : If you issue MRS after issuing EMRS, EMRS value will be reset . So you have to issue EMRS after issuing MRS. 3-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SDRAM CONTROLLER S3C24A0 RISC MICROPROCESSOR SDRAM Memory Interface Examples XpADDR0 XpADDR1 XpADDR2 XpADDR3 XpADDR4 XpADDR5 XpADDR6 XpADDR7 XpADDR8 XpADDR9 XpADDR10 XpADDR11 XpADDR13 XpADDR14 XpDQM0 XpDQM1 XpCKE XpSCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE XpDATA0 XpDATA1 XpDATA2 XpDATA3 XpDATA4 XpDATA5 XpDATA6 XpDATA7 XpDATA8 XpDATA9 XpDATA10 XpDATA11 XpDATA12 XpDATA13 XpDATA14 XpDATA15 XpCSN0 XpRASn XpCASn XpWEn Figure 3-1. Memory Interface with 16-bit SDRAM (4Mx16, 4banks) XpADDR0 XpADDR1 XpADDR2 XpADDR3 XpADDR4 XpADDR5 XpADDR6 XpADDR7 XpADDR8 XpADDR9 XpADDR10 XpADDR11 XpADDR13 XpADDR14 XpDQM0 XpDQM1 XpCKE XpSCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE XpDATA0 XpDATA1 XpDATA2 XpDATA3 XpDATA4 XpDATA5 XpDATA6 XpDATA7 XpDATA8 XpDATA9 XpDATA10 XpDATA11 XpDATA12 XpDATA13 XpDATA14 XpDATA15 XpCSN0 XpRASn XpCASn XpWEn XpADDR0 XpADDR1 XpADDR2 XpADDR3 XpADDR4 XpADDR5 XpADDR6 XpADDR7 XpADDR8 XpADDR9 XpADDR10 XpADDR11 XpADDR13 XpADDR14 XpDQM2 XpDQM3 XpCKE XpSCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE XpDATA16 XpDATA17 XpDATA18 XpDATA19 XpDATA20 XpDATA21 XpDATA22 XpDATA23 XpDATA24 XpDATA25 XpDATA26 XpDATA27 XpDATA28 XpDATA29 XpDATA30 XpDATA31 XpCSN0 XpRASn XpCASn XpWEn Figure 3-2. Memory Interface with 16-bit SDRAM (4Mx16 * 2ea, 4banks) 3-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDRAM CONTROLLER SCLK SCKE Trc ADDR Ra Ca Rb Cb BA Ba Ba Ba Bb Bb A10/AP Ra Rb nSCS Trp nRAS nCAS Trcd nWE DATA (CL2) Da Db Dc Dd Da Db Dc Dd DATA (CL3) Da Db Dc Dd Da Db Dc Dd DQM Row Active(A bank) Read (A bank) (CL = 2 or CL = 3, BL = 4) Bank A Precharge Row Active(B bank) Write (B bank) Figure 3-3. SDRAM Timing Diagram 3-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SDRAM CONTROLLER S3C24A0 RISC MICROPROCESSOR SDRAM CONFIGURATION REGISTER Register SDRAM_BANKCFG Address 0x40C40000 R/W R/W Description Port 1 SDRAM configuration register Reset Value 0x9f0c SDRAM_BANKCFG Bit Description Driver Strength Control 00 = Full 01 = half Initial State DS [30:29] 10 = weak 11 = RFU 00 b Note : DS bit fields are only for mobile SDRAM. Temperature compensated self refresh control TCSR [28:27] 01 = 16 ~ 45 C 00 = 46 ~ 70 C o o 11 = 71 ~ 85 C 10 = -25 ~ 15 C Note: TCSR bit fields are only for mobile SDRAM. Partial array self refresh control 000 = 4banks 001 = 2banks 1banks 011 = Reserved 100 = Reserved Reserved 110 = Reserved 111 = Reserved Note: PASR bit fields are only for mobile SDRAM. Reserved 0 : not support sdram power down control 1 : support sdram power down control Row active time 0000 = 1-clock 0001 = 2-clock 0010 = 3-clock 0011 = 4clock 0100 = 5-clock 0101 = 6-clock 0110 = 7-clock 0111 = 8clock 1000 = 9-clock 1001 = 10-clock 1010 = 11-clock 1011 = 12clock 1100 = 13-clock 1101 = 14-clock 1110 = 15-clock 1111 = 16clock Row cycle time 0000 = 1-clock 0001 = 2-clock 0010 = 3-clock 0011 = 4clock 0100 = 5-clock 0101 = 6-clock 0110 = 7-clock 0111 = 8clock 1000 = 9-clock 1001 = 10-clock 1010 = 11-clock 1011 = 12clock 1100 = 13-clock 1101 = 14-clock 1110 = 15-clock 1111 = 16clock RAS to CAS delay 00 = 1-clock 01 = 2-clock 10 = 3-clock 11 = 4-clock 0 010 = 101 = 00b o o 00b PASR [26:24] Reserved PWRDN [23:21] [20] Tras [19:16] 1001b Trc [15:12] 1001b Trcd [11:10] 11b 3-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDRAM CONTROLLER Trp [9:8] Row pre-charge time 00 = 1-clock 01 = 2-clock 10 = 3-clock 11 = 4-clock 11b DENSITY1 [7:6] SDRAM base component density of bank 1 00 = 16Mbit 01 = 64Mbit 10 = 128Mbit 11 = 256Mbit and 512Mbit SDRAM base component density of bank 0 00 = 16Mbit 01 = 64Mbit 10 = 128Mbit 11 = 256Mbit and 512Mbit 10 = 2-clock 11 = 3-clock CAS latency 00 = Reserved 01 = 1-clock Auto pre-charge control 0 = enable auto pre-charge Determine data bus width 0 = 32-bit 00b DENSITY0 [5:4] 00b CL AP DW [3:2] [1] [0] 11b 10b 00b 1 = disable auto pre-charge 1 = 16-bit Note: SDRAM_BANKCFG register should not be written when the SDRAM controller is busy. The controller status bit, BUSY in SDRAM_BANKCON register, can be used to check if the controller is idle. SDRAM CONTROL REGISTER Register SDRAM_BANKCON Address 0x40C40004 R/W R/W Description Port 1 SDRAM control register Reset Value 0x00 SDRAM_BANKCON Reserved BUSY Bit [31:4] [3] Reserved Description SDRAM controller status bit (read only) 0 = IDLE 1 = BUSY Write buffer control 0 = Disable 1 = Enable Note: Write buffer mentioned above is in SDRAM controller. If write buffer is disabled, data is written to the external SDRAM memory immediately. If write buffer is enabled, data is flushed to the external SDRAM memory when write buffer is full. Initial State 0b 0b WBUF [2] 0b INIT [1:0] SDRAM initialization control 00 = Normal operation 01 = Issue PALL command 10 = Issue MRS command 11 = Issue EMRS command note: EMRS command is only for mobile SDRAM. 00b REFRESH CONTROL REGISTER Register SDRAM_REFRESH Address 0x40C40008 R/W R/W Description SDRAM refresh control register Reset Value 0x0020 3-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SDRAM CONTROLLER S3C24A0 RISC MICROPROCESSOR SDRAM_REFRESH Bit SDRAM refresh cycle. Description Example: Refresh period is 15.6us, and HCLK is 66MHz. The value of REFCYC is as follows: -6 6 REFCYC = 15.6 x 10 x 66 x 10 = 1029 Initial State REFCYC [15:0] 100000b NOTES 3-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER NAND FLASH CONTROLLER (PRELIMINARY) OVERVIEW Recently, a NOR flash memory gets high in price while an SDRAM and a NAND flash memory get moderate, motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM. S3C24A0 boot code can be executed on an external NAND flash memory. In order to support NAND flash boot loader, the S3C24A0 is equipped with an internal SRAM buffer called `Steppingstone'. When booting, the first 4 KBytes of the NAND flash memory will be loaded into Steppingstone and the boot code loaded into Steppingstone will be executed. Generally, the boot code will copy NAND flash content to SDRAM. Using hardware ECC, the NAND flash data validity will be checked. Upon the completion of the copy, the main program will be executed on the SDRAM. FEATURES -- Support up to 2Gbit Nand Flash Memory. -- Support 256/512/1K/2K byte page, 3,4 or 5 address cycle NAND Flash memory -- Auto boot mode : The boot code is transferred into Steppingstone during reset. After the transfer, the boot code will be executed on the Steppingstone. -- Auto load mode : Support automatically one or more page load from Flash Memory to Steppingstone -- Auto store mode : Support automatically one page store to Flash Memory from Steppingstone -- Software mode : User can directly access NAND flash memory, for example this feature can be used in read/erase/program NAND flash memory -- Memory bus interface : 8 / 16-bit NAND flash memory interface bus -- Hardware ECC generation, detection and indication (Software correction) -- SFR I/F : Support Little Endian Mode, Byte/half word/word access -- SteppingStone I/F : Support Little Endian, Byte/half word/word access -- The Steppingstone 4-KB internal SRAM buffer can be used for another purpose after NAND flash booting 4-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 NAND FLASH CONTROLLER S3C24A0 RISC MICROPROCESSOR PIN CONFIGURATION Here is a configuration of NAND Flash Controller of S3C24A0. Users can select configuration of NAND Flash Memory according to the table below. There is some differences between conventional NAND Flash Memory and New Advance Flash Memory. So users have to select the configuration properly. Advance Flash Page size 0 Bus width 0 1 0 1 0 1 0 1 Real page size 256Byte 256Word 512Byte 1KByte 1KByte 1KWord 2KByte 4KByte Organization 16bitX1 8bitX1 8bitX2 16bitX1 8bitX1 8bitX2 0 1 0 1 1 Advance Flash 0 1 Address cycle 0 1 0 1 Real cycle 3CYCLE(256M) 4CYCLE(512M) 4CYCLE(1G) 5CYCLE(2G) Table 4-1 Advance NAND Flash Controller Configuration (word means 16-bit in this table) 4-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER BLOCK DIAGRAM ECC Gen. NAND FLASH SFR CONTROL & AHB Slave I/F STATE MACHINE INTERFACE nCE CLE ALE nRE nWE R/nB0 R/nB1 I/O0~I/O15 SYSTEM BUS SteppingStone Controller SteppingStone (SRAM : 4KB) Figure 4-1 NAND Flash Controller Block Diagram BOOT LOADER FUNCTION When power-on or system reset is occurred, the NAND Flash controller loads automatically the 4-KBytes boot loader codes. After loading the boot loader codes, the boot loader code is executed on the steppingstone. AUTO BOOT CORE ACCESS (BOOT CODE) STEPPINGSTONE (4 KB BUFFER) NAND FLASH CONTROLLER SPECIAL FUNCTION REGISTERS NAND FLASH MEMORY USER ACCESS Figure 4-2 NAND Flash Controller Boot Loader Block Diagram 4-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 NAND FLASH CONTROLLER S3C24A0 RISC MICROPROCESSOR OPERATION MODE AUTO LOAD/STORE MODE CORE ACCESS STEPPINGSTONE (4 KB BUFFER) USER ACCESS SPECIAL FUNCTION REGISTERS NAND FLASH CONTROLLER NAND FLASH MEMORY S/W MODE Figure 4-3 NAND Flash Controller Operation Mode Block Diagram Figure 4-3 describes all operation modes of the NAND Flash controller. The NAND Flash controller controls the Auto load and store page(s) by using the steppingstone automatically in auto load or store mode. In software mode, you can access the NAND Flash Memory directly using the command, address and data register. TACLS TWRPH0 TWRPH1 TACLS TWRPH0 TWRPH1 HCLK Flash_CLE Flash_ALE Flash_nWE Flash_I/O COMMAND ADDRESS Figure 4-4 Auto Mode Timing Diagram (TACLS = 1, TWRPH0 = 0, TWRPH1 = 0) 4-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER AUTO LOAD MODE Auto load function supports automatically load the page(s) of the NAND Flash Memory to steppingstone up to 4KBytes. You can specify the load start address of the steppingstone and how many pages are loaded. AUTO LOAD PROGRAMMING GUIDE 1) Set command (read command), address (of the page you read), and configuration and control value. 2) Set the MODE bit of the controller register to 0b01(auto load start) 3) Once you set the MODE bit to auto mode, the NAND Flash controller automatically load the page(s) you specify from the NAND Flash Memory. 4) When auto loading is completed, the MODE is reset to 0b00 and the LoadDone bit of the status register is set. Also you can know this event by using auto load done interrupt NOTE: The NAND Flash Controller only load main area data (256 or 512 bytes), not the spare area data. So you need to access the spare area, you have to use the software mode (refer to the Software mode). TWRPH0 TWRPH1 TWRPH0 TWRPH0 TWRPH1 TWRPH0 TWRPH1 HCLK Flash_nRE Flash_I/O 1st Data 2nd Data N-1th Data Nth Data Flash_RnB Figure 4-5 NAND Flash Controller Auto Load Timing Diagram (TWRPH0 = 0, TWRPH1 = 0) AUTO STORE MODE Auto store function supports automatically store a page from the steppingstone to the NAND Flash Memory. You can specify the store start address of the steppingstone. In auto store mode, only one page store is supported. AUTO STORE PROGRAMMING GUIDE 1) Set command (1st program command), address (of the page you store), configuration and control value. 2) Set MODE bit of the controller register to 0b10(auto store start) 3) Once you set MODE bit to the auto store mode, the NAND Flash controller automatically store a page to the NAND Flash Memory. 4-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 NAND FLASH CONTROLLER S3C24A0 RISC MICROPROCESSOR 4) When auto storing is completed, the MODE is reset to 0b00 and the StoreDone bit of the status register is set. Also you can know this event by using auto store done interrupt NOTE: The NAND Flash Controller only store main area data (256 or 512 bytes), not the spare area data. So you need to access the spare area, you have to use the software mode (refer to the Software mode). TWRPH0 TWRPH1 TWRPH0 TWRPH0 TWRPH1 TWRPH0 TWRPH1 HCLK Flash_nWE Flash_I/O 1st DATA 2nd DATA N-1th DATA Nth DATA Flash_RnB Figure 4-6 NAND Flash Controller Auto Store Timing Diagram (TWRPH0 =0, TWRPH1 = 0) SOFTWARE MODE In the software mode, you can fully access the NAND Flash controller. The NAND Flash Controller supports direct access interface with the NAND Flash Controller. 1) The writing to the command register = the NAND Flash Memory command cycle 2) The writing to the address register = the NAND Flash Memory the address cycle 3) The writing to the data register = write data to the NAND Flash Memory (write cycle) 4) The reading from the data register = read data from the NAND Flash Memory (read cycle) 5) The reading main ECC registers and Spare ECC registers = read data from the NAND Flash Memory NOTE: In the software mode, you have check the Flash_RnB status input pin by using polling or interrupt. 4-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER STEPPING STONE (4K-Byte SRAM) The NAND Flash controller uses Steppingstone as the buffer in the auto load and store mode. Also you can use this area for another purpose, if you don't use auto load and store function. For the best performance, if you need to move the content of the NAND Flash Memory to SDRAM, We recommend that you use DMA burst transfer(source address : Steppingstone, destination address : SDRAM). The NAND Flash Controller supports that the NAND Flash controller and other masters can access the steppingstone concurrently. For example, 1K-byte of the steppingstone area have valid data, and the NAND Flash Controller is moving data from the NAND Flash Memory to Steppingstone(Area : 1K ~ 4K-Byte). You can move 0 ~ 1K-Byte data to the other memory area using DMA burst transfer(DMA burst tranfer is the best solution for the high speed). ERROR CORRECTION CODE NAND Flash controller has four ECC (Error Correction Code) modules. The two ECC modules (one for data[7:0] and the other for data[15:8]) can be used for (up to) 2048 bytes ECC Parity code generation, and the others(one for data[7:0] and the other for data[15:8]) can be used for (up to) 16 bytes ECC Parity code generation. 28bit ECC Parity Code = 22bit Line parity + 6bit Column Parity 14bit ECC Parity Code = 8bit Line parity + 6bit Column Parity DATA7 ECC0 ECC1 ECC2 ECC3 P64 P1024 P4 DATA6 P64' P1024' P4' DATA5 P32 P512 P2 DATA4 P32' P512' P2' DATA3 P16 P256 P1 DATA2 P16' P256' P1' DATA1 P8 P128 P2048 DATA0 P8' P128' P2048' 0 P8192 P8192' P4096 P4096' 0 0 0 Table 4-2 2K Byte Main Area ECC Parity Code Assignment Table DATA7 DATA6 P16' DATA5 P8 DATA4 P8' DATA3 P4 DATA2 P4' DATA1 P2 DATA0 P2' 0 ECC0 ECC1 P16 P1 P1' P64 P64' P32 P32' 0 Table 4-3 16 Byte SPARE AREA ECC Parity Code Assignment Table ECC MODULE FEATURES 1) In auto load & auto store mode, ECC module generates automatically ECC parity code. 2) In software mode, ECC generation is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit of the Control register. ECC PROGRAMMING GUIDE 1) In auto store mode In auto store mode, ECC module generates automatically ECC parity code for main data(256 or 512 4-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 NAND FLASH CONTROLLER S3C24A0 RISC MICROPROCESSOR bytes), not for spare area data. After auto store is completed, you may need to recode the ECC parity code generated to the spare area of NAND Flash Memory. In this case, you just do read the first, second and third ECC status registers and writes to the spare area. 2) In auto load mode In auto load mode, ECC module also generates automatically ECC parity code for main data. After auto load is completed, you may need to check that the content of NAND flash memory have no bit error. In this case, you just do read the first, second and third ECC value from the spare area through the main data area ecc0, ecc1 and ecc2 register. 3) In Software mode A. In software mode, ECC module generates ECC parity code for all read / write data. So you have to reset ECC value before read or write data using the InitECC bit of the Control register and have to set the MainECCLock bit of the control register to `0'. MainECCLock and SpareECCLock bit control whether ECC Parity code is generated or not. After you reset ECC parity code. Whenever you read or write data, the ECC module generate ECC parity code on this data. B. C. After you finished read or write all page data. Set the MainECCLock bit to `1'. ECC Parity code is locked and the value of the ECC status register isn't changed. From now as described in auto store & load mode, you can use these values to record to the spare area or check the bit error. NAND FLASH MEMORY CONFIGURATIONS Figure 4-7 ~ Figure 4-9 discribe the configuration of NAND flash memory. If you use NAND flash memory as a boot memroy, you can use one of the these memory configruration. But if you use NAND flash memory as a I/O memory not a boot memory, you have to connect nGCS[0] signal to Boot ROM memory. In these case you can use NF_RnB[1] signal which is used as a selection signal of NAND flash memory. Also the NF_RnB[1] is internally fixed `H'. RnB0 nFRE nFCE CLE ALE nFWE R/ B RE CE CLE ALE WE I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Figure 4-7 8-bit NAND Flash Memory Interface 4-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER RnB0 nFRE nFCE CLE ALE nFWE R/ B RE CE CLE ALE WE I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] RnB1 nFRE nFCE CLE ALE nFWE R/ B RE CE CLE ALE WE I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] Figure 4-8 Two 8-bit NAND Flash Memory Interface RnB0 nFRE nFCE CLE ALE nFWE R/ B RE CE CLE ALE WE I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Figure 4-9 16-bit NAND Flash Memory Interface 4-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 NAND FLASH CONTROLLER S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER SPECIAL REGISTERS CONFIGURATION REGISTER Register NFCONF Address 0x40C00000 R/W R/W Description NAND Flash Configuration register Reset Value 0x00XF100X NFCONF Reserved Advance Flash Bit [23] [22] Reserved Description Supports 1G & 2G Advance Flash Memory This bit indicates whether external memory is new version or not nCE High Hold Time to break the sequential read cycle Used only boot loader & auto load function Duration = HCLK * (TCEH+1) Reserved CLE & ALE duration Setting Value (0~7) Duration = HCLK * TACLS Reserved TWRPH0 duration Setting Value (0~7) Duration = HCLK * ( TWRPH0+1 ) 0 : External Flash Memories are not X16 device 1 : External Flash Memory is X16 device (READ ONLY) TWRPH1 duration Setting Value (0~7) Duration = HCLK * ( TWRPH1+1 ) Hardware Flash_nCE control 0 : Do not supports Flash_nCE control(Manual set) 1 : Supports Flash_nCE control NAND Flash Memory I/O bus width 0 : 8-bit bus (RnB0) 1 : 16-bit bus(RnB0 and RnB1) Auto Load Page Size of NAND Flash Memory 0 : 256/1K Bytes, 1 : 512/2K Bytes, Address Cycle of NAND Flash Memory 0 : 3/4 address cycle 1 : 4/5 address cycle Initial State 00 H/W Set TCEH [21:16] 0x3F Reserved TACLS Reserved TWRPH0 X16 Device TWRPH1 Hardware nCE [15] [14:12] [11] [10:8] [7] [6:4] [3] 0 001 0 110 0 110 1 Bus Width [2] H/W Set Page Size Address Cycle [1] [0] H/W Set H/W Set 4-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER CONTROL REGISTER Register NFCONT Address 0x40C00004 R/W R/W Description NAND Flash control register Description The address of the steppingstone to read or write when auto loading or storing Note: the bit [17:16] are fixed to zero. Illegal access interrupt control 0 : Disable interrupt 1 : Enable interrupt In Auto load, Data load completion interrupt control 0 : Disable interrupt 1 : Enable interrupt In Auto store, Data store completion interrupt control 0 : Disable interrupt 1 : Enable interrupt RnB status input signal transition interrupt control 0 : Disable RnB interrupt 1 : Enable RnB interrupt RnB transition detection configuration 0 : Detect low to high 1 : Detect high to low Lock Spare area ECC generation 0 : Unlock 1 : Lock Lock Main data area ECC generation 0 : Unlock 1 : Lock Initialize ECC decoder/encoder(Write-only) 0: 1 : Initialize ECC decoder/encoder NAND Flash Memory Flash_nCE control 0 : NAND flash chip enable(Active LOW) 1 : NAND flash chip disable (After AUTO Load / Store, nCE will be inactive) Note: It is controlled automatically in Auto Load / Store mode. You must control this value in Software mode. But if HW_nCE is set to 1, also controlled by H/W. Auto load page size configuration (0 ~ 7) Size = Setting value + 1 Lock-tight configuration 0: Disable 1 : Enable Note: Once you set this bit to 1, you can't clear this. In this state, you can only read. Lock configuration 0: Disable 1: Enable NAND Flash controller operating mode selection 00 = Disable all mode 01 = Auto load mode 10 = Auto store mode 11 = Software Mode Reset Value 0x0384 Initial State 0x00 NFCONT LdStrAddr Bit [27:16] EnbIllegalAccINT EnbLoadINT EnbStoreINT EnbRnBINT RnB_TransMode SpareECCLock MainECCLock InitECC [15] [14] [13] [12] [11] [10] [9] [8] 0 0 0 0 0 1 1 0 Reg_nCE [7] 1 LoadPageSize Lock-tight [6:4] [3] 000 0 Lock Mode [2] [1:0] 1 00 4-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 NAND FLASH CONTROLLER S3C24A0 RISC MICROPROCESSOR COMMAND REGISTER Register NFCMMD Address 0x40C00008 R/W R/W Bit [15:8] Description NAND Flash command set register Description NAND Flash memory 2 command value nd Reset Value 0x00 Initial State - NFCMMD NFCMMD1 NFCMMD0 [7:0] NAND Flash memory command value 0x00 nd NOTE: When you use Advance Flash memory, it has 2 cycle read command (h30). So If you want to do auto load you have to set the value at the REG_CMMD1. ADDRESS REGISTER Register NFADDR Address 0x40C0000C R/W Description Reset Value 0x0000XX00 Initial State 0x00 0x00 0xXX R/W NAND Flash address set register Bit Description NAND Flash memory address value3 (This value is only used at 4th or 5th address cycle) NAND Flash memory address value2 NAND Flash memory address value1 NFADDR NFADDR3 NFADDR 2 NFADDR 1 NFADDR 0 [31:24] [23:16] [15:8] [7:0] NAND Flash memory address value0 0x00 In Software mode, Only this value is used for Flash_IO NOTE: Advance Flash's 1st and 2nd address is always column address. It means you don't need to care about 1st and 2nd address. So, When you want to do auto load or store, you can set the address from REG_ADDR1 to REG_ADDR2 for 4 cycle address memory and from REG_ADDR1 to REG_ADDR3 for 5 cycle address memory. DATA REGISTER Register NFDATA Address 0x40C00010 Bit [15:8] [7:0] R/W R/W Description NAND Flash data register Description NAND Flash read/program data value for I/O[15:8] NAND Flash read/program data value for I/O[7:0] In case of write: Programming data In case of read: Reading data. These values are only used in Software mode. Reset Value 0xXXXX Initial State 0xXX 0xXX NF_DATA NFDATA1 NFDATA0 4-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER MAIN DATA AREA ECC0 REGISTER Register Address R/W R/W Description NAND Flash ECC register for main data read Description 1 ECC for I/O[15:8] 1st ECC for I/O[ 7:0] NOTE: In Software mode, Read this register when you need to read 1st ECC value from NAND flash memory st Reset Value 0x00000000 Initial State 0x00 0x00 NFMECCDATA0 0x40C00014 NFMECCDATA0 ECCData0_1 ECCData0_0 Bit [15:8] [7:0] MAIN DATA AREA ECC1 REGISTER Register NFMECCDATA1 NFMECCDATA1 ECCData1_1 ECCData1_0 Address 0x40C00018 Bit [15:8] [7:0] nd R/W Description Reset Value 0x00000000 Initial State 0x00 0x00 R/W NAND Flash ECC register for main data read Description 2 ECC for I/O[15:8] 2nd ECC for I/O[ 7:0] NOTE: In Software mode, Read this register when you need to read 2nd ECC value from NAND flash memory MAIN DATA AREA ECC2 REGISTER Register Address R/W Description Reset Value 0x00000000 Initial State 0x00 0x00 NFMECCDATA2 0x40C0001C R/W NAND Flash ECC register for main data read NFMECCDATA2 ECCData2_1 ECCData2_0 Bit [15:8] [7:0] rd Description 3 ECC for I/O[15:8] 3rd ECC for I/O[ 7:0] NOTE: In Software mode, Read this register when you need to read 3rd ECC value from NAND flash memory MAIN DATA AREA ECC3 REGISTER Register Address R/W Description Reset Value 0x00000000 NFMECCDATA3 0x40C00020 R/W NAND Flash ECC register for main data read( Advance Flash memory have 4byte ECC code ) NFMECCDATA3 ECCData3_1 ECCData3_0 Bit [15:8] [7:0] th Description 4 ECC for I/O[15:8] 4thECC for I/O[ 7:0] NOTE: In Software mode, Read this register when you need to read 4th ECC value from NAND flash memory Initial State 0x00 0x00 4-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 NAND FLASH CONTROLLER S3C24A0 RISC MICROPROCESSOR SPARE AREA ECC0 REGISTER Register Address R/W Description Reset Value 0x00000000 Initial State 0x00 0x00 NFSECCDATA0 0x40C00024 R/W NAND Flash ECC register for spare area data read NFSECCDATA0 SPARE ECCData0_1 SPARE ECCData0_0 Bit [15:8] [7:0] st Description 1 ECC for I/O[15:8] 1st ECC for I/O[ 7:0] NOTE: In Software mode, Read this register when you need to read 1st ECC value from NAND flash memory SPARE AREA ECC1 REGISTER Register Address R/W Description Reset Value 0x00000000 Initial State 0x00 0x00 NFSECCDATA1 0x40000028 R/W NAND Flash ECC register for spare area data read NFSECCDATA1 SPARE ECCData1_1 SPARE ECCData1_0 Bit [15:8] [7:0] nd Description 2 ECC for I/O[15:8] 2nd ECC for I/O[ 7:0] NOTE: In Software mode, Read this register when you need to read 2nd ECC value from NAND flash memory 4-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER NF_CONF STATUS REGISTER Register NFSTAT Address 0x40C0002C R/W Description Reset Value 0xXX00 Initial State 0 R/W NAND Flash operation status register Bit [16] Description Once Lock or Lock-tight is enabled, The illegal access (program, erase ...) to the memory makes this bit set. To clear this value write `1' 0 : Illegal access is not detected 1 : Illegal access is detected When Auto load operation is completed, this value set and issue interrupt if enabled. To clear this value write `1' 0 : Auto load completion is not detected 1 : Auto load completion is detected When Auto store operation is completed, this value set and issue interrupt if enabled. To clear this value write `1' 0 : Auto store completion is not detected 1 : Auto store completion is detected When RnB transition is occurred, this value set and issue interrupt if enabled. To clear this value write `1' 0 : RnB transition is not detected 1 : RnB transition is detected The status of Flash_nCE output pin (Read-only) The status of Flash_RnB1 input pin (Read-only) 0 : NAND Flash memory busy 1 : NAND Flash memory ready to operate The status of Flash_RnB0 input pin (Read-only) 0 : NAND Flash memory busy 1 : NAND Flash memory ready to operate SteppingStone access address (Read-only) This address indicates which part of the memory is accessed by the NAND Flash controller and is valid in auto load / store mode NFSTAT IllegalAccess AutoLoadDone [15] 0 AutoStoreDone [14] 0 RnB_TransDetect [13] 0 Flash_nCE Flash_RnB1 [12] [11] 1 X Flash_RnB0 [10] X STON_A2 [9:0] 0x00 4-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 NAND FLASH CONTROLLER S3C24A0 RISC MICROPROCESSOR ECC0 STATUS REGISTER Register NFESTAT0 NFESTAT0 SErrorDataNo SErrorBitNo MErrorDataNo MErrorBitNo SpareError Address 0x40C00030 Bit [24:21] [20:18] [17:7] [6:4] [3:2] R/W R/W Description NAND Flash ECC Status register for I/O [7:0] Description In spare area, Indicates which number data is error In spare area, Indicates which bit is error In main data area, Indicates which number data is error In main data area, Indicates which bit is error Reset Value 0x00000000 Initial State 00 000 0x00 000 00 Indicates whether spare area bit fail error occurred 00 : No Error 01 : 1-bit error(correctable) 10 : Multiple error 11 : ECC area error MainError [1:0] Indicates whether main data area bit fail error occurred 00 00 : No Error 01 : 1-bit error(correctable) 10 : Multiple error 11 : ECC area error NOTE: The above values are only valid when both NFMECCDATAn(NFSECCDATAn) and NFMECCn(NFSECC) have valid value. ECC1 STATUS REGISTER Register NFESTAT1 NFESTAT1 SErrorDataNo SErrorBitNo MErrorDataNo MErrorBitNo SpareError Address 0x40C00034 Bit [24:21] [20:18] [17:7] [6:4] [3:2] R/W R/W Description NAND Flash ECC Status register for I/O [15:8] Description In spare area, Indicates which number data is error In spare area, Indicates which bit is error In main data area, Indicates which number data is error In main data area, Indicates which bit is error Reset Value 0x00000000 Initial State 00 000 0x00 000 00 Indicates whether spare area bit fail error occurred 00 : No Error 01 : 1-bit error(correctable) 10 : Multiple error 11 : ECC area error MainError [1:0] Indicates whether main data area bit fail error occurred 00 00 : No Error 01 : 1-bit error(correctable) 10 : Multiple error 11 : ECC area error NOTE: The above values are only valid when both NFMECCDATAn(NFSECCDATAn) and NFMECCn(NFSECC) have valid value. 4-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER MAIN DATA AREA ECC0 STATUS REGISTER Register NFMECC0 Address 0x40C00038 Bit [31:24] [23:16] [15:8] [7:0] R/W R Description NAND Flash ECC register for I/O [7:0] Description ECC: Error Correction Code #3 ECC: Error Correction Code #2 ECC: Error Correction Code #1 ECC: Error Correction Code #0 Reset Value 0xXXXXXX Initial State 0xXX 0xXX 0xXX 0xXX NFMECC0 MECC0_3 MECC0_2 MECC0_1 MECC0_0 MAIN DATA AREA ECC1 STATUS REGISTER Register NFMECC1 Address 0x40C0003C R/W R Bit [31:24] [23:16] [15:8] [7:0] Description NAND Flash ECC register for data[15:8] Description ECC: Error Correction Code #3 ECC: Error Correction Code #2 ECC: Error Correction Code #1 ECC: Error Correction Code #0 Reset Value 0xXXXXXX Initial State 0xXX 0xXX 0xXX 0xXX NFMECC1 MECC1_3 MECC1_2 MECC1_1 MECC1_0 SPARE AREA ECC STATUS REGISTER Register NFSECC Address 0x40C00040 R/W R Bit [31:24] [23:16] [15:8] [7:0] Description NAND Flash ECC register for I/O [15:0] Description Spare area ECC1 Status for I/O[15:8] Spare area ECC0 Status for I/O[15:8] Spare area ECC1 Status for I/O[7:0] Spare area ECC0 Status for I/O[7:0] Reset Value 0xXXXXXX Initial State 0xXX 0xXX 0xXX 0xXX NFSECC SECC1_1 SECC1_0 SECC0_1 SECC0_0 4-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 NAND FLASH CONTROLLER S3C24A0 RISC MICROPROCESSOR START BLOCK ADDRESS REGISTER Register NFSBLK NFSBLK SBLK_ADDR2 SBLK_ADDR1 SBLK_ADDR0 Address 0x40C00044 Bit [23:16] [15:8] [7:0] rd R/W R/W Description NAND Flash programmable start block address Description Reset Value 0x000000 Initial State The 3 block address of the block erase operation 0x00 The 2nd block address of the block erase operation 0x00 0x00 The 1st block address of the block erase operation (Only bit [7:5] are valid when External Memory is old version and Only bit [7:6] are valid when External Memory is new version) NOTE: Advance Flash's block Address starts from 3 address cycle. So Block address register only need 3Byte. END BLOCK ADDRESS REGISTER Register NFEBLK NFEBLK EBLK_ADDR2 EBLK_ADDR1 EBLK_ADDR0 Address 0x40C00048 Bit [23:16] [15:8] [7:0] rd R/W R/W Description NAND Flash programmable end block address Description Reset Value 0x000000 Initial State The 3 block address of the block erase operation 0x00 nd The 2 block address of the block erase operation 0x00 st 0x00 The 1 block address of the block erase operation (Only bit [7:5] are valid when External Memory is old version and Only bit [7:6] are valid when External Memory is new version) NOTE: Advance Flash's block Address starts from 3 address cycle. So Block address register only need 3Byte. 4-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR NAND FLASH CONTROLLER NOTES 4-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR BUS MATRIX BUS MATRIX OVERVIEW S3C24A0 MATRIX provides the interface between dual AHB bus and Memory sub-system. It is used for achieving high system performance by accessing various kinds of memory (SDRAM, SRAM, Flash Memory, ROM etc) from different AHB bus (one is for system and the other is for image) at the same time. S3C24A0 have two MATRIX cores because it has two memory ports, and each MATRIX can select the priority between rotation type and fixed type. User can select which one is excellent for improving system performance. Figure 5-1 shows the configuration of MATRIX and Memory sub-system of S3C24A0. It also shows the model of external memory. Both AHB bus can access all MATRIX core and MATRIX core is dedicated each memory port respectively. So it can operate separately at the same time. It's a key of MATRIX. External Memory SFR SROM/ NFCON SROMC/ NFLASHC AHB-S MATRIX CORE0 SROM SROM SDRAMC SDRAM AHB-I MATRIX CORE1 SDRAM MATRIX External memory interface Figure 5-1 Configuration of MATRIX and Memory sub-system 5-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 BUS MATRIX S3C24A0 RISC MICROPROCESSOR SPECIAL FUNCTION REGISTERS SROMC/NFLASHC ARBITER PRIORITY REGISTER (PRIORITY0) Register PRIORITY0 Address 0X40CE0000 R/W R/W priority control register Description Reset Value 0x0000_0000 PRIORITY0 FIX_PRI_TYP Bit [1] Description Priority type 0: Provide higher priority to S-Bus when user set fixed priority 1: Provide higher priority to I-Bus when user set fixed priority Priority type 0: Fixed priority 1: Rotating priority Initial State 0 PRI_TYP [0] 0 SDRAMC ARBITER PRIORITY REGISTER (PRIORITY1) Register PRIORITY1 Address 0X40CE0004 R/W R/W priority control register Description Reset Value 0x0000_0000 PRIORITY1 FIX_PRI_TYP Bit [1] PRI_TYP [0] Description Priority type 0: Provide higher priority to S-Bus when user set fixed priority 1: Provide higher priority to I-Bus when user set fixed priority Priority type 0: Fixed priority 1: Rotating priority Initial State 0 0 5-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT CONTROLLER OVERVIEW The interrupt controller in S3C24A0 receives the requests for interrupt services from 61 interrupt sources. These interrupt sources are provided by internal peripherals such as a DMA controller, UART and IIC, etc. Among these interrupt sources, the UART0 and UART1 error interrupts are 'OR'ed to the interrupt controller. And, two interrupts from a Display/Post processor , two interrupts from Timer3/Timer4, and four interrupts from DMA controller are individually `OR'ed to the interrupt controller. Also, the IrDA/Memory stick interrupts, two interrupts from ADC/PENUP/PENDN are individually `OR'ed to the interrupt controller. The role of the interrupt controller is to ask for the FIQ or IRQ interrupt requests to the ARM926EJ core after the arbitration process when there are multiple interrupt requests from internal peripherals and external interrupt request pins. The arbitration process is performed by the hardware priority logic and the result is written to the interrupt pending register and users notice that register to know which interrupt has been requested. FUNCTIONAL DESCRIPTION F-BIT AND I-BIT OF PSR (PROGRAM STATUS REGISTER) If the F-bit of PSR (program status register in ARM926EJ CPU) is set to 1, the CPU does not accept the FIQ (fast interrupt request) from the interrupt controller. If I-bit of PSR (program status register in ARM926EJ CPU) is set to 1, the CPU does not accept the IRQ (interrupt request) from the interrupt controller. So, to enable the interrupt reception, the F-bit or I-bit of PSR has to be cleared to 0 and also the corresponding bit of INTMSK has to be set to 0. INTERRUPT MODE ARM926EJ has 2 types of interrupt mode, FIQ or IRQ. All the interrupt sources determine the mode of interrupt to be used at interrupt request. 6-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR INTERRUPT PENDING REGISTER S3C24A0 has two interrupt pending resisters. The one is source pending register(SRCPND), the other is interrupt pending register(INTPND). These pending registers indicate whether or not an interrupt request is pending. When the interrupt sources request interrupt service the corresponding bits of SRCPND register are set to 1, at the same time the only one bit of INTPND register is set to 1 automatically after arbitration process. If interrupts are masked, the corresponding bits of SRCPND register are set to 1, but the bit of INTPND register is not changed. When a pending bit of INTPND register is set, the interrupt service routine starts whenever the I-flag or F-flag is cleared to 0. The SRCPND and INTPND registers can be read and written, so the service routine must clear the pending condition by writing a 1 to the corresponding bit in SRCPND register first and then clear the pending condition in INTPND registers same method. INTERRUPT MASK REGISTER Indicates that an interrupt has been disabled if the corresponding mask bit is 1. If an interrupt mask bit of INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is generated, the source pending bit will be set. 6-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT SOURCES Interrupt controller supports 61 interrupt sources as shown in below table. Among the 32 interrupt sources, each interrupt source corresponding to INT_ADC, INT_PCM_MSTICK, INT_AC97_NFLASH, INT_DMA_PBUS, INT_DMA_GBUS, INT_DMA_MBUS, INT_UART0, INT_UART1, and INT_CAMPRO is an `OR'ed interrupt which combines multiple subinterrupt sources connected to the corresponding interrupt sources, and provides a single interrupt source to interrupt controller. Sources INT_ADC_ PENUP_DOWN INT_RTC INT_VLX_SPI1 INT_IrDA_MSTICK INT_IIC INT_USBH INT_USBD INT_AC97_NFLASH INT_UART1 INT_SPI0 INT_SDI INT_DMA INT_ MODEM INT_CAMIF_PREVIEW INT_UART0 INT_WDT_BATFLT INT_CAMIF_CODEC INT_LCD_POST INT_TIMER3,4 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_KEYPAD INT_ME INT_MC INT_DCTQ INT_TIC EINT15_18 EINT11_14 EINT7_10 EINT3_6 EINT0_2 Descriptions ADC EOC/Pen up/Pen down interrupt RTC alarm interrupt SPI1 interrupt IrDA/MSTICK Interrupt IIC interrupt USB Host interrupt USB Device interrupt AC97/NFLASH interrupt UART1 Interrupt ( ERR,RXD,TXD) SPI0 interrupt SDI interrupt DMA channels for S-bus interrupt MODEM Interface interrupt Camera Interface interrupt UART0 Interrupt ( ERR,RXD,TXD) WDT/BATFLT interrupt Camera Interface interrupt LCD/POST interrupt Timer3/4 interrupt Timer2 interrupt Timer1 interrupt Timer0 interrupt Keypad interrupt ME interrupt MC interrupt DCTQ interrupt RTC Time tick interrupt External interrupt 15-18 External interrupt 11-14 External interrupt 7-10 External interrupt 3-6 External interrupt 0-2 Arbiter Group ARB5 ARB5 ARB5 ARB5 ARB4 ARB4 ARB4 ARB4 ARB4 ARB4 ARB3 ARB3 ARB3 ARB3 ARB3 ARB3 ARB2 ARB2 ARB2 ARB2 ARB2 ARB2 ARB1 ARB1 ARB1 ARB1 ARB1 ARB1 ARB0 ARB0 ARB0 ARB0 6-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in the following figure. ARBITER0 REQ1/EINT0_2 REQ2/EINT3_6 REQ3/EINT7_10 REQ4/EINT11_14 REQ1/EINT15_18 REQ2/INT_TIC REQ3/DCTQ REQ4/INT_MC REQ5/INT_ME REQ6/INT_Keypad REQ1/INT_TIMER0 REQ2/INT_TIMER1 REQ3/INT_TIMER2 REQ4/INT_TIMER3,4 REQ5/INT_LCD_POST REQ6/INT_CAMIF_CODEC REQ1/INT_WDT_BATFLT REQ2/INT_UART0 REQ3/INT_CAMIF_PREVIEW REQ4/INT_MODEM REQ5/INT_DMA REQ6/INT_SDI REQ1/INT_SPI0 REQ2/INT_UART1 REQ3/INT_AC97_NFLASH REQ4/INT_USBD REQ5/INT_USBH REQ6/INT_IIC REQ1/INT_IrDA_MSTICK REQ2/INT_VLC_SPI1 REQ3/INT_RTC REQ4/INT_ADC_PENUP_PENDN ARBITER1 ARBITER2 ARM IRQ ARBITER6 ARBITER3 ARBITER4 ARBITER5 Figure 6-1. Priority Generating Block 6-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER Interrupt Priority Each arbiter can handle six interrupt requests based on the one bit arbiter mode control(ARB_MODE) and two bits of selection control signals(ARB_SEL) as follows: If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5. If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5. If ARB_SEL bits are 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5. If ARB_SEL bits are 11b, the priority order is REQ0, REQ4, REQ1, REQ2, REQ3, and REQ5. Note that REQ0 of an arbiter is always the highest priority, and REQ5 is the lowest one. In addition, by changing the ARB_SEL bits, we can rotate the priority of REQ1 - REQ4. Here, if ARB_MODE bit is set to 0, ARB_SEL bits are not automatically changed, thus the arbiter operates in the fixed priority mode. (Note that even in this mode, we can change the priority by manually changing the ARB_SEL bits.). On the other hand, if ARB_MODE bit is 1, ARB_SEL bits are changed in rotation fashion, e.g., if REQ1 is serviced, ARB_SEL bits are changed to 01b automatically so as to make REQ1 the lowest priority one. The detailed rule of ARB_SEL change is as follows. If REQ0 or REQ5 is serviced, ARB_SEL bits are not changed at all. If REQ1 is serviced, ARB_SEL bits are changed to 01b. If REQ2 is serviced, ARB_SEL bits are changed to 10b. If REQ3 is serviced, ARB_SEL bits are changed to 11b. If REQ4 is serviced, ARB_SEL bits are changed to 00b. VECTORED INTERRUPT MODE (ONLY FOR IRQ) S3C24A0 has a vectored interrupt mode, to reduce the interrupt latency time. If ARM926EJ receives the IRQ interrupt request from the interrupt controller, it executes an instruction at 0x00000018. The LDR instruction which loads to PC the address written in Vector Address Register, one of special function registers in Interrupt controller, is located at 0x00000018. That is, @0x0000_0018 : LDR PC, [VAR] where, VAR is the special function register at 0x4020_002c of interrupt controller. 6-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR The LDR instruction lets the program counter be the vector table address corresponding to each interrupt source. The user program code must locate the branch instruction, which branches to the corresponding ISR (interrupt service routine) at each vector table address. For example, If TIMER1 is IRQ, the LDR instruction at 0x00000018 which lets PC be 0x0000004c, is executed . 0x0000004c is automatically written to Vector Address Register by hardware logic. And the branch instruction, which jumps to the ISR, is located at 0x0000004c. Vector number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Vector name Interrupt vector address EINT0_2 EINT3_6 EINT7_10 EINT11_14 EINT15_18 INT_TICK INT_DCTQ INT_MC INT_ME INT_KEYPAD INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3,4 INT_LCD_POST INT_CAMIF_CODEC INT_WDT_BATFLT INT_UART0 INT_CAMIF_PREVIEW INT_MODEM INT_DMA 0x0000_0020 0x0000_0024 0x0000_0028 0x0000_002c 0x0000_0030 0x0000_0034 0x0000_0038 0x0000_003c 0x0000_0040 0x0000_0044 0x0000_0048 0x0000_004c 0x0000_0050 0x0000_0054 0x0000_0058 0x0000_005c 0x0000_0060 0x0000_0064 0x0000_0068 0x0000_006c 0x0000_0070 6-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER 21 22 23 24 25 26 27 28 29 30 31 INT_SDI INT_SPI0 INT_UART1 INT_AC97_NFLASH INT_USBD INT_USBH INT_IIC INT_IrDA_MSTICK INT_VLX_SPI1 INT_RTC INT_ADC_PENUP_DOWN 0x0000_0074 0x0000_0078 0x0000_007c 0x0000_0080 0x0000_0084 0x0000_0088 0x0000_008c 0x0000_0090 0x0000_0094 0x0000_0098 0x0000_009c SPECIAL FUNCTION REGISTERS There are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. All the interrupt requests from the interrupt sources are first registered in the source pending register. They are divided into two groups based on the interrupt mode register, i.e., one FIQ request and the remaining IRQ requests. Arbitration process is performed for the multiple IRQ requests based on the priority register. SOURCE PENDING REGISTER (SRCPND) SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. By reading this register, we can see the interrupt sources waiting for their requests to be serviced. Note that each bit of SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the INTMASK register. In addition, it is not affected by the priority logic of interrupt controller. In the interrupt service routine for a specific interrupt source, the corresponding bit of SRCPND register has to be cleared to get the interrupt request from the same source correctly. If you return from the ISR without clearing the bit, interrupt controller operates as if another interrupt request comes in from the same source. In other words, if a specific bit of SRCPND register is set to 1, it is always considered as a valid interrupt request waiting to be serviced. 6-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR The specific time to clear the corresponding bit depends on the user's requirement. The bottom line is that if you want to receive another valid request from the same source you should clear the corresponding bit first, and then enable the interrupt. You can clear a specific bit of SRCPND register by writing a data to this register. It clears only the bit positions of SRCPND corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are with no change. Register SRCPND Address 0X40200000 R/W R/W Description Indicates the interrupt request status. 0 = The interrupt has not been requested 1 = The interrupt source has asserted the interrupt request Reset Value 0x00000000 NOTE : When the user clear a interrupt pending, specific bit of SRCPND and INTPND, has to clear the bit of SRCPND 6-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER SRCPND INT_ADC_PENUP_DOW N INT_RTC INT_VLX_SPI1 Bit [31] Description 0 = Not requested, (SUBSRCPND) 0 = Not requested, 0 = Not requested, (SUBSRCPND) 0 = Not requested, (SUBSRCPND) 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, (SUBSRCPND) 0 = Not requested, (SUBSRCPND) 0 = Not requested, 0 = Not requested, 0 = Not requested, (SUBSRCPND) 0 = Not requested, 0 = Not requested, 0 = Not requested, (SUBSRCPND) 0 = Not requested, (SUBSRCPND) 0 = Not requested, 0 = Not requested, (SUBSRCPND) 0 = Not requested, (SUBSRCPND) 0 = Not requested, 1 = Requested Initial State 0 [30] [29] 1 = Requested 1 = Requested 0 0 INT_IrDA_MSTICK [28] 1 = Requested 0 INT_IIC INT_USBH INT_USBD INT_AC97_NFLASH [27] [26] [25] [24] 1 = Requested 1 = Requested 1 = Requested 1 = Requested 0 0 0 0 INT_UART1 [23] 1 = Requested 0 INT_SPI0 INT_SDI INT_DMA [22] [21] [20] 1 = Requested 1 = Requested 1 = Requested 0 0 0 INT_MODEM INT_CAMIF_PREVIEW INT_UART0 [19] [18] [17] 1 = Requested 1 = Requested 1 = Requested 0 0 0 INT_WDT_BATFLT [16] 1 = Requested 0 INT_CAMIF_CODEC INT_LCD_POST [15] [14] 1 = Requested 1 = Requested 0 0 INT_TIMER3,4 [13] 1 = Requested 0 INT_TIMER2 [12] 1 = Requested 0 6-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR INT_TIMER1 INT_TIMER0 INT_KEYPAD INT_ME INT_MC INT_DCTQ INT_TIC EINT15_18 EINT11_14 EINT7_10 EINT3_6 EINT0_2 [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 0 0 0 0 0 0 0 0 0 0 0 0 6-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT MODE REGISTER (INTMOD) This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt). Note that at most only one interrupt source can be serviced in the FIQ mode in the interrupt controller. (You should use the FIQ mode only for the urgent interrupt.) Thus, only one bit of INTMOD can be set to 1 at most. This register is write-only one, thus it cannot be read out. Register INTMOD Address 0X40200004 R/W R/W Description Interrupt mode regiseter. 0 = IRQ mode 1 = FIQ mode Reset Value 0x00000000 NOTE : If an interrupt mode is set to FIQ mode in INTMOD register, FIQ interrupt will not affect INTPND and INTOFFSET registers. The INTPND and INTOFFSET registers are valid only for IRQ mode interrupt source. INTMOD INT_ADC_PENUP_DOWN INT_RTC INT_VLX_SPI1 INT_IrDA_MSTICK INT_IIC INT_USBH INT_USBD INT_AC97_NFLASH INT_UART1 INT_SPI0 INT_SDI INT_DMA INT_MODEM Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] Description 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 6-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR INT_CAMIF_PREVIEW INT_UART0 INT_WDT_BATFLT INT_CAMIF_CODEC INT_LCD_POST INT_TIMER3,4 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_KEYPAD INT_ME INT_MC INT_DCTQ INT_TIC EINT15_18 EINT11_14 EINT7_10 EINT3_6 EINT0_2 [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT MASK REGISTER (INTMSK) Each of the 32 bits in the interrupt mask register is related to an interrupt source. If you set a specific bit to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU. (Note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced. Register INTMSK Address 0X40200008 R/W R/W Description Determines which interrupt source is masked. The masked interrupt source will not be serviced. 0 = Interrupt service is available 1 = Interrupt service is masked Reset Value 0xffffffff INTMSK INT_ADC_PENUP_DOW N INT_RTC INT_VLX_SPI1 INT_IrDA_MSTICK INT_IIC INT_USBH INT_USBD INT_AC97_NFLASH INT_UART1 INT_SPI0 INT_SDI INT_DMA INT_MODEM INT_CAMIF_PREVIEW INT_UART0 Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] Description 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked Initial State 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR INT_WDT_BATFLT INT_CAMIF_CODEC INT_LCD_POST INT_TIMER3,4 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_KEYPAD INT_ME INT_MC INT_DCTQ INT_TIC EINT15_18 EINT11_14 EINT7_10 EINT3_6 EINT0_2 [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY REGISTER (PRIORITY) Register Address R/W Description IRQ priority control register Reset Value 0x7f PRIORITY 0X4020000C R/W PRIORITY ARB_SEL6 Bit [20:19] Description Arbiter 6 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 5 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 Arbiter 4 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 3 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 2 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 1 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 0 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 Arbiter 6 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 5 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 4 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 3 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 2 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Initial State 0 ARB_SEL5 [18:17] 0 ARB_SEL4 [16:15] 0 ARB_SEL3 [14:13] 0 ARB_SEL2 [12:11] 0 ARB_SEL1 [10:9] 0 ARB_SEL0 [8:7] 0 ARB_MODE6 [6] 1 ARB_MODE5 [5] 1 ARB_MODE4 [4] 1 ARB_MODE3 [3] 1 ARB_MODE2 [2] 1 6-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR ARB_MODE1 [1] Arbiter 1 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 0 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable 1 ARB_MODE0 [0] 1 6-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT PENDING REGISTER (INTIPND) Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request is the highest priority one that is unmasked and waits for the interrupt to be serviced. Since INTPND is located after the priority logic, only one bit can be set to 1 at most, and that is the very interrupt request generating IRQ to CPU. In interrupt service routine for IRQ, you can read this register to determine the interrupt source to be serviced among 32 sources. Like the SRCPND, this register has to be cleared in the interrupt service routine after clearing SRCPND register. We can clear a specific bit of INTPND register by writing a data to this register. It clears only the bit positions of INTPND corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are with no change. Register INTPND Address 0X40200010 R/W R/W Description Indicates the interrupt request status. 0 = The interrupt has not been requested 1 = The interrupt source has asserted the interrupt request Reset Value 0x00000000 NOTE : If the FIQ mode interrupt is occurred, the corresponding bit of INTPND will not be turned on. Because the INTPND register is available only for IRQ mode interrupt. INTPND INT_ADC_PENUP_DOWN INT_RTC INT_VLX_SPI1 INT_IrDA_MSTICK INT_IIC INT_USBH INT_USBD INT_AC97_NFLASH INT_UART1 INT_SPI0 Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] Description 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested Initial State 0 0 0 0 0 0 0 0 0 0 6-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR INT_SDI INT_DMA INT_MODEM INT_CAMIF_PREVIEW INT_UART0 INT_WDT_BATFLT INT_CAMIF_CODEC INT_LCD_POST INT_TIMER3,4 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_KEYPAD INT_ME INT_MC INT_DCTQ INT_TIC EINT15_18 EINT11_14 EINT7_10 EINT3_6 EINT0_2 [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT OFFSET REGISTER (INTOFFSET) The number in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND. Register INTOFFSET Address 0X40200014 R/W R Description Indicates the IRQ interrupt request source Reset Value 0x00000000 INT Source INT_ADC_PENUP_DOWN INT_RTC INT_VLX_SPI1 INT_IrDA_MSTICK INT_IIC INT_USBH INT_USBD INT_AC97_NFLASH INT_UART1 INT_SPI0 INT_SDI INT_DMA INT_MODEM INT_CAMIF_PREVIEW INT_UART0 INT_WDT_BATFLT The OFFSET value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Source INT_CAMIF_CODEC INT_LCD_POST INT_TIMER3,4 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_KEYPAD INT_ME INT_MC INT_DCTQ INT_TIC EINT15_18 EINT11_14 EINT7_10 EINT3_6 EINT0_2 The OFFSET value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOTE : If the FIQ mode interrupt is occurred, the INTOFFSET will not be affected. Because the INTOFFSET register is available only for IRQ mode interrupt. 6-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR SUB SOURCE PENDING REGISTER (SUBSRCPND) You can clear a specific bit of SUBSRCPND register by writing a data to this register. It clears only the bit positions of the SUBSRCPND corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are with no change. Register SUBSRCPND Address 0X402000018 R/W R/W Description Indicates the interrupt request status. 0 = The interrupt has not been requested 1 = The interrupt source has asserted the interrupt request Reset Value 0x00000000 SUBSRCPND Reserved INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_VLX INT_SPI1 INT_AC97 INT_NFLASH INT_DISP_FRAME INT_ADC INT_PENDN INT_PENUP INT_DISP_FIFO INT_POST INT_BATFLT INT_WDT Bit [31:29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] Description 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER INT_TIMER4 INT_TIMER3 Reserved INT_MSTICK INT_IrDA INT_ERR1 INT_TXD1 INT_RXD1 INT_ERR0 INT_TXD0 INT_RXD0 [12] [11] [10:8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Not requested, 0 = Not requested, 1 = Requested 1 = Requested - 0 0 0 0 0 0 0 0 0 0 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 6-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR INTERRUPT SUB MASK REGISTER (INTSUBMSK) Each of the 32 bits in the interrupt mask register is related to an interrupt source. If you set a specific bit to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU. (Note that even in such a case, the corresponding bit of SUBSRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced. Register INTSUBMSK Address 0X4020001C R/W R/W Description Determines which interrupt source is masked. The masked interrupt source will not be serviced. 0 = Interrupt service is available 1 = Interrupt service is masked Reset Value 0x1fffffff INTSUBMSK reserved INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_VLX INT_SPI1 INT_AC97 INT_NFLASH INT_DISP_FRAME INT_ADC INT_PENDN INT_PENUP INT_DISP_FIFO INT_POST INT_BATFLT Bit [31:29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] Description 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked Initial State 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROLLER INT_WDT INT_TIMER4 INT_TIMER3 Reserved INT_MSTICK INT_IrDA INT_ERR1 INT_TXD1 INT_RXD1 INT_ERR0 INT_TXD0 INT_RXD0 [13] [12] [11] [10:8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Service available, 0 = Service available, 0 = Service available, 1 = Masked 1 = Masked 1 = Masked - 1 1 1 1 1 1 1 1 1 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 6-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 INTERRUPT CONTROLLER S3C24A0 RISC MICROPROCESSOR VECTORED INTERRUPT MODE REGISTER (VECT_INT_MODE) This register is used to indicate if the vectored interrupt mode is enabled. If you set a bit[0] to 1, the vectored interrupt mode will be enabled. Register Address R/W Description R/W Indicates if the vectored interrupt mode is enabled. 0 = Nonvectored interrupt mode 1 = Vectored interrupt mode Reset Value 0x00000000 VECT_INT_MODE 0X40200020 VECT_INT_MODE reserved Vect_int_mode Bit [31:1] [0] Description 0 = vectored interrupt mode disable 1 = vectored interrupt mode enable Initial State 0 VECTOR ADDRESS REGISTER (VAR) This register is used to provide the interrupt vector address to which the program control branches. If IRQ occurs, the LDR instruction at 0x0000_0018 let PC be the value written in this register. If VECT_INT_MODE[0] is set to `0', the address in NONVECT_ADDR is passed to this register, and if VECT_INT_MODE[0] is set to `1', the address in VECT_ADDR is passed to this register. Register VAR Address 0X4020002C R/W Description R Provides the interrupt vector address Reset Value - VAR Var Bit [31:0] Description Provides the interrupt vector address Initial State - 6-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MOCROPROCESSOR PWM TIMER PWM TIMER(Preliminary) OVERVIEW The S3C24A0 has five 16-bit timers. The timer 0, 1, 2, 3 have PWM function(Pulse Width Modulation). Timer 4 has an internal timer only with no output pins. Timer 0 has a dead-zone generator, which is used with a large current device. Timer 0 and timer 1 share an 8-bit prescaler, timers 2, 3 and 4 share the other 8-bit prescaler. Each timer has a clock-divider which has 4 different divided signals (1/2, 1/4, 1/8, 1/16). Each timer block receives its own clock signals from the clock-divider, which receives the clock from the corresponding 8-bit prescaler. The 8-bit prescaler is programmable and divides the PCLK according to the loading value, which is stored in TCFG0 and TCFG1 registers. The timer count buffer register(TCNTBn) has an initial value which is loaded into the down-counter when the timer is enabled. The timer compare buffer register(TCMPBn) has an initial value which is loaded into the compare register to be compared with the down-counter value. This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed. Each timer has its own 16-bit down counter, which is driven by the timer clock. When the down counter reaches zero, the timer interrupt request is generated to inform the CPU that the timer operation has been completed. When the timer counter reaches zero, the value of corresponding TCNTBn is automatically loaded into the down counter to continue the next operation. However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode, the value of TCNTBn will not be reloaded into the counter. The value of TCMPBn is used for PWM (pulse width modulation). The timer control logic changes the output level when the down-counter value matches the value of the compare register in the timer control logic. Therefore, the compare register determines the turn-on time(or turn-off time) of an PWM output. FEATURE -- Five 16-bit timers -- Two 8-bit prescalers & Two 4-bit divider -- Programmable duty control of output waveform (PWM) -- Auto-reload mode or one-shot pulse mode -- Dead-zone generator 7-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PWM TIMER S3C24A0 RISC MICROPROCESSOR TCMPB0 TCNTB0 Dead Zone Generator Control Logic0 TOUT0 4:1 MUX Dead Zone PCLK 8-Bit Prescaler 1/2 1/4 1/8 1/16 Clock Divider TCMPB1 TCNTB1 TOUT1 4:1 MUX TCMPB2 4:1 MUX Control Logic1 Dead Zone TCNTB2 TOUT2 Control Logic2 1/2 1/4 8-Bit Prescaler 1/8 1/16 Clock Divider TCMPB3 TCNTB3 TOUT3 Control Logic3 Figure 7-1. 16-bit PWM Timer Block Diagram 4:1 MUX 4:1 MUX TCNTB4 Control Logic4 No Pin 7-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MOCROPROCESSOR PWM TIMER PWM TIMER OPERATION PRESCALER & DIVIDER An 8-bit prescaler and 4-bit divider make the following output frequencies: 4-bit divider settings 1/2 ( PCLK = 55 MHz ) 1/4 ( PCLK = 55 MHz ) 1/8 ( PCLK = 55 MHz ) 1/16 ( PCLK = 55 MHz ) BASIC TIMER OPERATION minimum resolution (prescaler = 0) 0.0363 us (27.5000 MHz ) 0.0727 us (13.7500 MHz ) 0.1454us ( 6.8750 MHz ) 0.2909 us ( 3.4375MHz ) maximum resolution (prescaler = 255) 9.3090 us (107.4219 KHz ) 18.6181 us (53.7109 KHz ) 37.2363 us (26.8554KHz ) 74.4729 us (13.4277 KHz ) maximum interval (TCNTBn = 65535) 0.6100 sec 1.2201 sec 2.4403 sec 4.8806 sec start bit=1 timer is started TCNTn=TCMPn auto-reload TCNTn=TCMPn timer is stopped. TCMPn 1 0 TCNTn 3 3 2 1 0 2 1 0 0 TCNTBn=3 TCMPBn=1 manual update=1 auto-reload=1 auto-reload=0 TCNTBn=2 interrupt request interrupt request TCMPBn=0 manual update=0 auto-reload=1 TOUTn command status Figure 7-2. Timer operations A timer (except the timer ch-5) has TCNTBn, TCNTn, TCMPBn and TCMPn. TCNTBn and TCMPBn are loaded into TCNTn and TCMPn when the timer reaches 0. When TCNTn reaches 0, the interrupt request will occur if the interrupt is enabled. (TCNTn and TCMPn are the names of the internal registers. The TCNTn register can be read from the TCNTOn register) 7-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PWM TIMER S3C24A0 RISC MICROPROCESSOR AUTO-RELOAD & DOUBLE BUFFERING S3C24A0 PWM Timers have a double buffering feature, which can change the reload value for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully. The timer value can be written into TCNTBn (Timer Count Buffer register) and the current counter value of the timer can be read from TCNTOn (Timer Count Observation register). If TCNTBn is read, the read value is not the current state of the counter but the reload value for the next timer duration. The auto-reload is the operation, which copies the TCNTBn into TCNTn when TCNTn reaches 0. The value, written into TCNTBn, is loaded to TCNTn only when the TCNTn reaches to 0 and auto-reload is enabled. If the TCNTn is 0 and the auto-reload bit is 0, the TCNTn does not operate any further. Write TCNTBn = 100 Start TCNTBn = 150 Write TCNTBn = 200 Auto-reload 150 100 100 200 Interrupt Figure 7-3. Example of Double Buffering Feature 7-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MOCROPROCESSOR PWM TIMER TIMER INITIALIZation using Manual UpdatE BIT and Inverter BIt Because an auto-reload operation of the timer occurs when the down counter reaches to 0, a starting value of the TCNTn has to be defined by the user at first. In this case, the starting value has to be loaded by the manual update bit. The sequence of starting a timer is as follows; 1) Write the initial value into TCNTBn and TCMPBn 2) Set the manual update bit of the corresponding timer. It is recommended to configure the inverter on/off bit. (whether use inverter or not) 3) Set start bit of corresponding timer to start the timer(At the same time, clear the manual update bit). Also, if the timer is stopped by force, the TCNTn retains the counter value and is not reloaded from TCNTBn. If new value has to be set, manual update has to be done. NOTE Whenever TOUT inverter on/off bit is changed, the TOUTn logic value will be changed whether or not the timer runs. Therefore, it is desirable that the inverter on/off bit is configured with the manual update bit. 7-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PWM TIMER S3C24A0 RISC MICROPROCESSOR EXAMPLE OF a TIMER OPERATION 1 2 3 4 6 79 10 TOUTn 50 110 40 40 20 60 5 8 11 Figure 7-4. Example of a Timer Operation The result of the following procedure is shown in Figure21-4; 1. Enable the auto-reload feature. Set the TCNTBn as 160 (50+110) and the TCMPBn as 110. Set the manual update bit and configure the inverter bit(on/off). The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn, respectively. And then, set TCNTBn and TCMPBn as 80 (40+40) and 40, respectively, to determine the next reload value. 2. Set the start bit, provided that manual_update is 0 and inverter is off and auto-reload is on. The timer starts counting down after latency time within the timer resolution. 3. When TCNTn has the same value with TCMPn, the logic level of TOUTn is changed from low to high. 4. When TCNTn reaches 0, the interrupt request is generated and TCNTBn value is loaded into a temporary register. At the next timer tick, TCNTn is reloaded with the temporary register value(TCNTBn). 5. In the ISR(Interrupt Service Routine), the TCNTBn and TCMPBn are set as 80 (20+60) and 60, respectively, which is used for the next duration. 6. When TCNTn has the same value as TCMPn, the logic level of TOUTn is changed from low to high. 7. When TCNTn reaches 0, TCNTn is reloaded automatically with TCNTBn. At the same time, the interrupt request is generated. 8. In the ISR (Interrupt Service Routine), auto-reload and interrupt request are disabled to stop the timer. 9. When the value of TCNTn is same as TCMPn, the logic level of TOUTn is changed from low to high. 10. Even when TCNTn reaches to 0, TCNTn is not any more reloaded and the timer is stopped because autoreload has been disabled. 11. No interrupt request is generated. 7-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MOCROPROCESSOR PWM TIMER PWM (Pulse Width Modulation) 60 50 40 30 30 Write TCMPBn = 60 Write TCMPBn = 50 Write TCMPBn = 40 Write TCMPBn = 30 Write TCMPBn = 30 Write TCMPBn = Next PWM Value Figure 7-5. Example of PWM PWM feature can be implemented by using the TCMPBn. PWM frequency is determined by TCNTBn. A PWM value is determined by TCMPBn in Figure 7-5. For a higher PWM value, decrease the TCMPBn value. For a lower PWM value, increase the TCMPBn value. If an output inverter is enabled, the increment/decrement may be reversed. Because of the double buffering feature, TCMPBn, for a next PWM cycle, can be written at any point in the current PWM cycle by ISR or something else 7-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PWM TIMER S3C24A0 RISC MICROPROCESSOR Output Level Control Inverter off Inverter on Initial State Period 1 Period 2 Timer Stop Figure 7-6. Inverter On/Off The following methods can be used to maintain TOUT as high or low.(assume the inverter is off) 1. Turn off the auto-reload bit. And then, TOUTn goes to high level and the timer is stopped after TCNTn reaches to 0. This method is recommended. 2. Stop the timer by clearing the timer start/stop bit to 0. If TCNTn TCMPn, the output level is high. If TCNTn >TCMPn, the output level is low. 3. TOUTn can be inverted by the inverter on/off bit in TCON. The inverter removes the additional circuit to adjust the output level. 7-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MOCROPROCESSOR PWM TIMER DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device. This feature is used to insert the time gap between a turn-off of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices turning on simultaneously, even for a very short time. TOUT0 is the PWM output. nTOUT0 is the inversion of the TOUT0. If the dead zone is enabled, the output wave form of TOUT0 and nTOUT0 will be TOUT0_DZ and nTOUT0_DZ, respectively. nTOUT0_DZ is routed to the TOUT1 pin. In the dead zone interval, TOUT0_DZ and nTOUT0_DZ can never be turned on simultaneously. TOUT0 nTOUT0 Deadzone Interval TOUT0_DZ nTOUT0_DZ Figure 7-7. The Wave Form When a Dead Zone Feature is Enabled 7-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PWM TIMER S3C24A0 RISC MICROPROCESSOR Dma request mode The PWM timer can generate a DMA request at every specific times. The timer keeps DMA request signal (nDMA_REQ) low until the timer receives the ACK signal. When the timer receives the ACK signal, it makes the request signal inactive. The timer, which generates the DMA request, is determined by setting DMA mode bits(in TCFG1 register). If one of timers is configured as DMA request mode, that timer does not generate an interrupt request. The others can generate interrupt normally. DMA mode configuration and DMA / interrupt operation DMA mode 0000 0001 0010 0011 0100 0101 0110 DMA request No select Timer0 Timer1 Timer2 Timer3 Timer4 No select Timer0 INT ON OFF ON ON ON ON ON Timer1 INT ON ON OFF ON ON ON ON Timer2 INT ON ON ON OFF ON ON ON Timer3 INT ON ON ON ON OFF ON ON Timer4 INT ON ON ON ON ON OFF ON PCLK INT4tmp DMAreq_en 101 nDMA_ACK nDMA_REQ INT4 Figure 7-8. The Timer4 DMA mode operation 7-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MOCROPROCESSOR PWM TIMER PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 Register TCFG0 Address 0x44000000 R/W R/W Description Configures the two 8-bit prescalers Reset Value 0x00000000 TCFG0 Reserved Dead zone length Prescaler 1 Prescaler 0 Bit [31:24] [23:16] [15:8] [7:0] Description These 8 bits determine the dead zone length. The 1 unit time of the dead zone length is equal to the 1 unit time of timer 0. These 8 bits determine prescaler value for Timer 2, 3 and 4 These 8 bits determine prescaler value for Timer 0 and 1 Initial State 0x00 0x00 0x00 0x00 7-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PWM TIMER S3C24A0 RISC MICROPROCESSOR TIMER CONFIGURATION REGISTER1 (TCFG1) Register TCFG1 Address 0x44000004 R/W R/W Description 5-MUX & DMA mode selecton register Reset Value 0x00000000 TCFG1 Reserved DMA mode Bit [31:24] [23:20] Description Select DMA request channel 0000 = No select(All interrupt) 0001 = Timer0 0010 = Timer1 0011 = Timer2 0100 = Timer3 0101 = Timer4 0110 = Reserved Select MUX input for PWM Timer4. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 Select MUX input for PWM Timer3. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 Select MUX input for PWM Timer2. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 Select MUX input for PWM Timer1. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 Select MUX input for PWM Timer0. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 Initial State 00000000 0000 MUX 4 [19:16] 0000 MUX 3 [15:12] 0000 MUX 2 [11:8] 0000 MUX 1 [7:4] 0000 MUX 0 [3:0] 0000 7-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MOCROPROCESSOR PWM TIMER TIMER CONTROL REGISTER (TCON) Register TCON Address 0x44000008 R/W R/W Description Timer control register Reset Value 0x00000000 TCON Timer 4 auto reload on/off Timer 4 manual update (note) Timer 4 start/stop Timer 3 auto reload on/off Timer 3 output inverter on/off Timer 3 manual update (note) Timer 3 start/stop Timer 2 auto reload on/off Timer 2 output inverter on/off Timer 2 manual update (note) Timer 2 start/stop Timer 1 auto reload on/off Timer 1 output inverter on/off Timer 1 manual update (note) Timer 1 start/stop Reserved Bit [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7:5] Description This bit determines auto reload on/off for Timer 4. 0 = One-shot 1 = Interval mode (auto reload) This bit determines the manual update for Timer 4. 0 = No operation 1 = Update TCNTB4 This bit determines start/stop for Timer 4. 0 = Stop 1 = Start for Timer 4 This bit determines auto reload on/off for Timer 3. 0 = One-shot 1 = Interval mode (auto reload) This bit determines output inverter on/off for Timer 3. 0 = Inverter off 1 = Inverter on for TOUT3 This bit determine manual update for Timer 3. 0 = No operation 1 = Update TCNTB3, TCMPB3 This bit determines start/stop for Timer 3. 0 = Stop 1 = Start for Timer 3 This bit determines auto reload on/off for Timer 2. 0 = One-shot 1 = Interval mode (auto reload) This bit determines output inverter on/off for Timer 2. 0 = Inverter off 1 = Inverter on for TOUT2 This bit determines the manual update for Timer 2. 0 = No operation 1 = Update TCNTB2, TCMPB2 This bit determines start/stop for Timer 2. 0 = Stop 1 = Start for Timer 2 This bit determines the auto reload on/off for Timer1. 0 = One-shot 1 = Interval mode (auto reload) This bit determines the output inverter on/off for Timer1. 0 = Inverter off 1 = Inverter on for TOUT1 This bit determines the manual update for Timer 1. 0 = No operation 1 = Update TCNTB1, TCMPB1 This bit determines start/stop for Timer 1. 0 = Stop 1 = Start for Timer 1 - initial state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - NOTE: This bit has to be cleared at next writing. 7-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PWM TIMER S3C24A0 RISC MICROPROCESSOR TCON(Continued) TCON Dead zone enable Timer 0 auto reload on/off Timer 0 output inverter on/off Timer 0 manual update (note) Timer 0 start/stop Bit [4] [3] [2] [1] [0] Description This bit determines the dead zone operation. 0 = Disable 1 = Enable This bit determines auto reload on/off for Timer 0. 0 = One-shot 1 = Interval mode(auto reload) This bit determines the output inverter on/off for Timer 0. 0 = Inverter off 1 = Inverter on for TOUT0 This bit determines the manual update for Timer 0. 0 = No operation 1 = Update TCNTB0, TCMPB0 This bit determines start/stop for Timer 0. 0 = Stop 1 = Start for Timer 0 initial state 0 0 0 0 0 NOTE: This bit has to be cleared at next writing. 7-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MOCROPROCESSOR PWM TIMER Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0, TCMPB0) Register TCNTB0 TCMPB0 Address 0x4400000C 0x44000010 R/W R/W R/W Description Timer 0 count buffer register Timer 0 compare buffer register Reset Value 0x00000000 0x00000000 TCMPB0 Timer 0 compare buffer register Bit [15:0] Description Setting compare buffer value for Timer 0 Initial State 0x00000000 TCNTB0 Timer 0 count buffer register Bit [15:0] Description Setting count buffer value for Timer 0 Initial State 0x00000000 TIMER 0 COUNT OBSERVATION REGISTER (TCNTO0) Register TCNTO0 Address 0x44000014 R/W R Description Timer 0 count observation register Reset Value 0x00000000 TCNTO0 Timer 0 observation register Bit [15:0] Description Setting count observation value for Timer 0 Initial State 0x00000000 7-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PWM TIMER S3C24A0 RISC MICROPROCESSOR TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1, TCMPB1) Register TCNTB1 TCMPB1 Address 0x44000018 0x4400001C R/W R/W R/W Description Timer 1 count buffer register Timer 1 campare buffer register Reset Value 0x00000000 0x00000000 TCMPB1 Timer 1 compare buffer register Bit [15:0] Description Setting compare buffer value for Timer 1 Initial State 0x00000000 TCNTB1 Timer 1 count buffer register Bit [15:0] Description Setting count buffer value for Timer 1 Initial State 0x00000000 Timer 1 Count Observation Register(TCNTO1) Register TCNTO1 Address 0x44000020 R/W R Description Timer 1 count observation register Reset Value 0x00000000 TCNTO1 Timer 1 observation register Bit [15:0] Description Setting count observation value for Timer 1 initial state 0x00000000 7-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MOCROPROCESSOR PWM TIMER TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2, TCMPB2) Register TCNTB2 TCMPB2 Address 0x44000024 0x44000028 R/W R/W R/W Description Timer 2 count buffer register Timer 2 campare buffer register Reset Value 0x00000000 0x00000000 TCMPB2 Timer 2 compare buffer register Bit [15:0] Description Setting compare buffer value for Timer 2 Initial State 0x00000000 TCNTB2 Timer 2 count buffer register Bit [15:0] Description Setting count buffer value for Timer 2 Initial State 0x00000000 TIMER 2 COUNT OBSERVATION REGISTER (TCNTO2) Register TCNTO2 Address 0x4400002C R/W R Description Timer 2 count observation register Reset Value 0x00000000 TCNTO2 Timer 2 observation register Bit [15:0] Description Setting count observation value for Timer 2 Initial State 0x00000000 7-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PWM TIMER S3C24A0 RISC MICROPROCESSOR TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3, TCMPB3) Register TCNTB3 TCMPB3 Address 0x44000030 0x44000034 R/W R/W R/W Description Timer 3 count buffer register Timer 3 campare buffer register Reset Value 0x00000000 0x00000000 TCMPB3 Timer 3 compare buffer register Bit [15:0] Description Setting compare buffer value for Timer 3 Initial State 0x00000000 TCNTB3 Timer 3 count buffer register Bit [15:0] Description Setting count buffer value for Timer 3 Initial State 0x00000000 TIMER 3 COUNT OBSERVATION REGISTER (TCNTO3) Register TCNTO3 Address 0x44000038 R/W R Description Timer 3 count observation register Reset Value 0x00000000 TCNTO3 Timer 3 observation register Bit [15:0] Description Setting count observation value for Timer 3 Initial State 0x00000000 7-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MOCROPROCESSOR PWM TIMER TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register TCNTB4 Address 0x4400003C R/W R/W Description Timer 4 count buffer register Reset Value 0x00000000 TCNTB4 Timer 4 count buffer register Bit [15:0] Description Setting count buffer value for Timer 4 Initial State 0x00000000 TIMER 4 COUNT OBSERVATION REGISTER (TCNTO4) Register TCNTO4 Address 0x44000040 R/W R Description Timer 4 count observation register Reset Value 0x00000000 TCNTO4 Timer 4 observation register Bit [15:0] Description Setting count observation value for Timer 4 Initial State 0x00000000 7-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 PWM TIMER S3C24A0 RISC MICROPROCESSOR NOTES 7-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR WATCHDOG TIMER WATCHDOG TIMER(Preliminary) OVERVIEW The S3C24A0 watchdog timer is used to resume the controller operation when it had been disturbed by malfunctions such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The watchdog timer generates the reset signal for 128 PCLK cycles. FEATURES -- Normal interval timer mode with interrupt request -- Internal reset signal is activated for 128 PCLK cycles when the timer count value reaches 0(time-out). 8-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 WATCHDOG TIMER S3C24A0 RISC MICROPROCESSOR WATCHDOG TIMER OPERATION The functional block diagram of the watchdog timer is shown in Figure 8-1. The watchdog timer uses PCLK as its only source clock. To generate the corresponding watchdog timer clock, the PCLK frequency is prescaled first, and the resulting frequency is divided again. MUX 1/16 1/32 PCLK 8-bit Prescaler 1/64 1/128 WTDAT Interrupt WTCNT (Down Counter) Reset Signal Generator RESET WTCON[15:8] WTCON[4:3] WTCON[2] WTCON[0] Figure 8-1. Watchdog Timer Block Diagram The prescaler value and the frequency division factor are specified in the watchdog timer control register, WTCON. The valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64, or 128. Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle: t_watchdog = 1/( PCLK / (Prescaler value + 1) / Division_factor ) WTDAT & WTCNT When the watchdog timer is enabled first, the value of WTDAT (watchdog timer data register) cannot be automatically reloaded into the WTCNT (timer counter). For this reason, an initial value must be written to the watchdog timer count register, WTCNT, before the watchdog timer starts. CONSIDERATION OF DEBUGGING ENVIRONMENT When S3C24A0 is in debug mode using Embedded ICE, the watchdog timer must not operate. The watchdog timer can determine whether or not the current mode is the debug mode from the CPU core signal (DBGACK signal). Once the DBGACK signal is asserted, the reset output of the watchdog timer is not activated when the watchdog timer is expired. 8-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR WATCHDOG TIMER WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL REGISTER (WTCON) Using the Watchdog Timer Control register, WTCON, you can enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. The Watchdog timer is used to resume the S3C24A0 restart on mal-function after power-on; if controller restart is not desired, the Watchdog timer should be disabled. If the user wants to use the normal timer provided by the Watchdog timer, please enable the interrupt and disable the Watchdog timer. Register WTCON Address 0x44100000 R/W R/W Description Watchdog timer control Register Reset Value 0x8021 WTCON Prescaler value Reserved Watchdog timer Bit [15:8] [7:6] [5] Description the prescaler value The valid range is from 0 to (28-1) Reserved. These two bits must be 00 in normal operation. Enable or disable bit of Watchdog timer. 0 = Disable 1 = Enable This two bits determines the clock division factor 00 : 16 01 : 32 10 : 64 11 : 128 Enable or disable bit of the interrupt. 0 = Disable 1 = Enable Reserved. This bit must be 0 in normal operation Enable or disable bit of Watchdog timer output for reset signal 1 : Asserts reset signal of the S3C24A0 at watchdog time-out 0 : Disables the reset function of the watchdog timer. Initial State 0x80 00 1 Clock select [4:3] 00 Interrupt generation [2] 0 Reserved Reset enable/disable [1] [0] 0 1 8-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 WATCHDOG TIMER S3C24A0 RISC MICROPROCESSOR WATCHDOG TIMER DATA REGISTER (WTDAT) The watchdog timer data register, WTDAT is used to specify the time-out duration. The content of WTDAT can not be automatically loaded into the timer counter at initial watchdog timer operation. However, the first time-out occurs by using 0x8000(initial value), after then the value of WTDAT will be automatically reloaded into WTCNT. Register WTDAT Address 0x44100004 R/W R/W Description Watchdog timer data Register Reset Value 0x8000 WTDAT count reload value Bit [15:0] Description Watchdog timer count value for reload. Initial State 0x8000 WATCHDOG TIMER COUNT REGISTER (WTCNT) The watchdog timer count register, WTCNT, contains the current count values for the watchdog timer during normal operation. Note that the content of the watchdog timer data register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially, so the watchdog timer count register must be set to an initial value before enabling it. Register WTCNT Address 0x44100008 R/W R/W Description Watchdog timer count Register Reset Value 0x8000 WTCNT Count value Bit [15:0] Description The current count value of the watchdog timer Initial State 0x8000 8-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR DMA DMA (Preliminary) OVERVIEW S3C24A0 supports four-channel DMA( Bridge DMA or peripheral DMA) controller that is located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. In other words, each channel can handle the following four cases: 1) both source and destination are in the system bus, 2) source is in the system bus while destination is in the peripheral bus, 3) source is in the peripheral bus while destination is in the system bus, 4) both source and destination are in the peripheral bus. The main advantage of DMA is that it can transfer the data without CPU intervention. The operation of DMA can be initiated by S/W, the request from internal peripherals or the external request pins. 9-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 DMA S3C24A0 RISC MICROPROCESSOR DMA request sources Each channel of DMA controller can select one of DMA request source among four DMA sources if H/W DMA request mode is selected by DCON register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.) The four DMA sources for each channel are as follows. Source0 Ch-0 Ch-1 Ch-2 Ch-3 nXDREQ0 Source1 UART0 Source2 I2SSDI Source3 PWM Timer Source4 USB device EP1 USB device EP2 USB device EP3 USB device EP4 Source5 AC97_PCMout Source6 MSTICK Source7 IrDA nXDREQ1 UART1 I2SSDO SPI AC97_PCMin AC97_PCMout IrDA UART0 I2SSDO SDMMC PWM Timer AC97_MICin AC97_PCMin Reserved UART1 SDMMC SPI Timer MSTICK AC97_MICin Reserved Table 9-1. DMA request sources for each channel Here, nXDREQ0 and nXDREQ1 represent two external sources(External Devices), and I2SSDO and I2SSDI represent IIS transmitting and receiving, respectively. DMA OPERATION The details of DMA operation can be explained using three-state FSM(finite state machine) as follows: State-1. State-2. State-3. As an initial state, it waits for the DMA request. If it comes, go to state-2. At this state, DMA ACK and INT REQ are 0. In this state, DMA ACK becomes 1 and the counter(CURR_TC) is loaded from DCON[19:0] register. Note that DMA ACK becomes 1 and remains 1 until it is cleared later. In this state, sub-FSM handling the atomic operation of DMA is initiated. The sub-FSM reads the data from the source address and then writes it to destination address. In this operation, data size and transfer size (single or burst) are considered. This operation is repeated until the counter(CURR_TC) becomes 0 in the whole service mode, while performed only once in a single service mode. The main FSM (this FSM) counts down the CURR_TC when the sub-FSM finishes each of atomic operation. In addition, this main FSM asserts the INT REQ signal when CURR_TC becomes 0 and the interrupt setting of DCON[28] register is set to 1. In addition, it clears DMA ACK if one of the following conditions are met. 1) CURR_TC becomes 0 in the whole service mode 2) atomic operation finishes in the single service mode. Note that in the single service mode, these three states of main FSM are performed and then stops, and waits for another DMA REQ. And if DMA REQ comes in all three states are repeated. Therefore, DMA ACK is asserted and then de-asserted for each atomic transfer. In contrast, in the whole service mode, main FSM waits at state-3 until CURR_TC becomes 0. Therefore, DMA ACK is asserted during all the transfers and then de-asserted when TC reaches 0. However, INT REQ is asserted only if CURR_TC becomes 0 regardless of the service mode (single service mode or whole service mode). 9-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR DMA EXTERNAL DMA DREQ/DACK PROTOCOL There are four types of external DMA request/acknowledge protocols. Each type defines how the signals like DMA request and acknowledge are related to these protocols. Basic DMA Timing The DMA service means paired Reads and Writes cycles during DMA operation, which is one DMA operation. The Fig. 9-1 shows the basic Timing in the DMA operation of the S3C24A0. The setup time and the delay time of XnXDREQ and XnXDACK are same in all the modes. If the completion of XnXDREQ meets its setup time, it is synchronized twice and then XnXDACK is asserted. After assertion of XnXDACK, DMA requests the bus and if it gets the bus it performs its operations. XnXDACK is deasserted when DMA operation finishes. XSCLK 9.3ns Setup XnXDREQ 9.3ns Setup Min. 2MCLK 6.6ns Delay XnXDACK Read Min. 3MCLK 6.8ns Delay Write Figure 9-1. Basic DMA Timing Diagram 9-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 DMA S3C24A0 RISC MICROPROCESSOR Demand/Handshake Mode Comparison - Related to the Protocol between XnXDREQ and XnXDACK These are two different modes related to the protocol between XnXDREQ and XnXDACK. Fig. 8-2 shows the differences between these two modes i.e., Demand and Handshake modes. At the end of one transfer(Single/Burst transfer), DMA checks the state of double-synched XnXDREQ. Demand mode If XnXDREQ remains asserted, the next transfer starts immediately. Otherwise it waits for XnXDREQ to be asserted. Handshake mode If XnXDREQ is deasserted, DMA deasserts XnXDACK in 2cycles. Otherwise it waits until XnXDREQ is deasserted. Caution : XnXDREQ has to be asserted(low) only after the deassertion(high) of XnXDACK. XSCLK Demand Mode XnXDREQ 2cycles 1st Transfer 2nd Transfer Write Read Write XnXDACK Double synch Read Handshake Mode XnXDREQ BUS Acquisiton Actual Transfer Read Write 2cycles Double synch 2cycles XnXDACK Figure 9-2. Demand/Handshake Mode Comparison 9-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR DMA Transfer Size There are two different transfer sizes; single and Burst 4. DMA holds the bus firmly during the transfer of these chunk of data, thus other bus masters can not get the bus. Burst 4 Transfer Size 4 sequential Reads and 4 sequential Writes are performed in the Burst 4 Transfer. * NOTE: Single Transfer size : One read and one write are performed. XSCLK XnXDREQ XnXDACK Double synch 3 cycles Read Read Read Read Write Write Write Write Figure 9-3. Burst 4 Transfer size 9-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 DMA S3C24A0 RISC MICROPROCESSOR Examples of possible cases Single service, Demand Mode, Single Transfer Size The assertion of XnXDREQ is need for every unit transfer(Single service mode), the operation continues while the XnXDREQ is asserted(Demand mode), and one pair of Read and Write(Single transfer size) is performed. XSCLK XnXDREQ XnXDACK Double synch Read Write Read Write Figure 9-4. Single service, Demand Mode, Single Transfer Size Single service/Handshake Mode, Single Transfer Size XSCLK XnXDREQ XnXDACK Double synch Read Write 2cycles Read Write Figure 9-5. Single service, Handshake Mode, Single Transfer Size Whole service/Handshake Mode, Single Transfer Size XSCLK XnXDREQ XnXDACK Double synch 3 cycles Read Write 2cycles Read Write 2cycles Read Write Figure 9-6. Whole service, Handshake Mode, Single Transfer Size 9-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR DMA DMA SPECIAL REGISTERS There are seven control registers for each DMA channel. (Since there are four channels, the total number of control registers is 28.) Four of them are to control the DMA transfer, and other three are to see the status of DMA controller. The details of those registers are as follows. DMA INITIAL SOURCE REGISTER (DISRC) Register DISRC0 DISRC1 DISRC2 DISRC3 Address 0x40400000 0x40500000 0x40600000 0x40700000 R/W R/W R/W R/W R/W Description DMA0 Initial Source Register DMA1 Initial Source Register DMA2 Initial Source Register DMA3 Initial Source Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DISRCn S_ADDR Bit [30:0] Description These bits are the base address (start address) of source data to transfer. This value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1. Initial State 0x00000000 DMA INITIAL SOURCE CONTROL REGISTER (DISRCC) Register DISRCC0 DISRCC1 DISRCC2 DISRCC3 Address 0x40400004 0x40500004 0x40600004 0x40700004 R/W R/W R/W R/W R/W Description DMA0 Initial Source Control Register DMA1 Initial Source Control Register DMA2 Initial Source Control Register DMA3 Initial Source Control Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DISRCn LOC Bit [1] Description Bit 1 is used to select the location of source. 0: the source is in the system bus (AHB), 1: the source is in the peripheral bus (APB) Initial State 0 INC [0] Bit 0 is used to select the address increment. 0 = Increment 1= Fixed If it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. If it is 1, the address is not changed after the transfer (In the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer). 0 9-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 DMA S3C24A0 RISC MICROPROCESSOR DMA INITIAL DESTINATION REGISTER (DIDST) Register DIDST0 DIDST1 DIDST2 DIDST3 Address 0x40400008 0x40500008 0x40600008 0x40700008 R/W R/W R/W R/W R/W Description DMA0 Initial Destination Register DMA1 Initial Destination Register DMA2 Initial Destination Register DMA3 Initial Destination Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DIDSTn D_ADDR Bit [30:0] Description These bits are the base address (start address) of destination for the transfer. This value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1. Initial State 0x00000000 DMA INITIAL DESTINATION CONTROL REGISTER (DIDSTC) Register DIDSTC0 DIDSTC1 DIDSTC2 DIDSTC3 Address 0x4040000C 0x4050000C 0x4060000C 0x4070000C R/W R/W R/W R/W R/W Description DMA0 Initial Destination Control Register DMA1 Initial Destination Control Register DMA2 Initial Destination Control Register DMA3 Initial Destination Control Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DIDSTn CHK_INT Bit [2] Description Select interrupt occurrence time when auto reload is setting 0: Interrupt will occur when TC reaches 0 1: Interrupt will occur after auto reload is performed. Initial State 0 LOC [1] Bit 1 is used to select the location of destination. 0: the destination is in the system bus (AHB). 1: the destination is in the peripheral bus (APB). 0 INC [0] Bit 0 is used to select the address increment. 0 = Increment 1= Fixed If it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. If it is 1, the address is not changed after the transfer (In the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer). 0 9-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR DMA DMA CONTROL REGISTER (DCON) Register DCON0 DCON1 DCON2 DCON3 Address 0x40400010 0x40500010 0x40600010 0x40700010 R/W R/W R/W R/W R/W Description DMA0 Control Register DMA1 Control Register DMA2 Control Register DMA3 Control Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DCONn DMD_HS Bit [31] 0 : demand mode is selected Description Select one between demand mode and handshake mode. 1 : handshake mode is selected. In both modes, DMA controller starts its transfer and asserts DACK for a given asserted DREQ. The difference between two modes is whether it waits for the de-asserted DACK or not. In handshake mode, DMA controller waits for the de-asserted DREQ before starting a new transfer. If it sees the de-asserted DREQ, it de-asserts DACK and waits for another asserted DREQ. In contrast, in the demand mode, DMA controller does not wait until the DREQ is de-asserted. It just deasserts DACK and then starts another transfer if DREQ is asserted. We recommend using handshake mode for external DMA request sources to prevent unintended starts of new transfers. Initial State 0 SYNC [30] Select DREQ/DACK synchronization. 0: DREQ and DACK are synchronized to PCLK (APB clock). 1: DREQ and DACK are synchronized to HCLK (AHB clock). Therefore, devices attached to AHB system bus, this bit has to be set to 1, while those attached to APB system, it should be set to 0. For the devices attached to external system, user should select this bit depending on whether the external system is synchronized with AHB system or APB system. 0 INT [29] Enable/Disable the interrupt setting for CURR_TC(terminal count) 0: CURR_TC interrupt is disabled. user has to look the transfer count in the status register. (i.e., polling) 1: interrupt request is generated when all the transfer is done (i.e., CURR_TC becomes 0). 0 TSZ [28] Select the transfer size of an atomic transfer (i.e., transfer performed at each time DMA owns the bus before releasing the bus). 0: a unit transfer is performed. 1: a burst transfer of length four is performed. 0 9-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 DMA S3C24A0 RISC MICROPROCESSOR DCONn Bit Description Initia l Stat e 0 SERVMODE [27] Select the service mode between single service mode and whole service mode. 0: single service mode is selected in which after each atomic transfer (single or burst of length four) DMA stops and waits for another DMA request. 1: whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0. In this mode, additional request is not required. Here, note that even in the whole service mode, DMA releases the bus after each atomic transfer and then tries to re-get the bus to prevent starving of other bus masters. HWSRCSEL [26:24] Select DMA request source for each DMA. Source 0 Source1 Source 2 Sourc e3 Source 4 USB device EP1 USB UART1 I2SSDO SPI device EP2 USB device EP3 USB device EP4 Source 5 Source 6 Source 7 000 Ch0 nXDRE Q0 UART0 I2SSDI PWM Timer AC97_ PCMout MSTICK IrDA Ch1 nXDRE Q1 AC97_ PCMin AC97_ PCMout IrDA Ch2 UART0 I2SSDO SD MMC PWM Timer AC97_ MICin AC97_ PCMin Reserve d Ch3 UART1 SD MMC SPI Timer MSTICK AC97_ MICin Reserve d This bits control the 8-1 MUX to select the DMA request source of each DMA. These bits have meanings if and only if H/W request mode is selected by DCONn[23]. SWHW_SEL [23] Select the DMA source between software (S/W request mode) and hardware (H/W request mode). 0: S/W request mode is selected and DMA is triggered by setting SW_TRIG bit of DMASKTRIG control register. 1: DMA source selected by bit[25:24] is used to trigger the DMA operation. RELOAD [22] Set the reload on/off option. 0: auto reload is performed when a current value of transfer count becomes 0 (i.e., all the required transfers are performed). 1: DMA channel(DMA REQ) is turned off when a current value of transfer count becomes 0. The channel on/off bit(DMASKTRIGn[1]) is set to 0(DREQ off) to prevent unintended further start of new DMA operation 0 0 9-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR DMA DSZ [21:20] Data size to be transferred. 00 = Byte 10 = Word 01 = Half word 11 = reserved 00 TC [19:0] Initial transfer count (or transfer beat). Note that the actual number of bytes that are transferred is computed by the following equation: DSZ x TSZ x TC, where DSZ, TSZ, and TC represent data size (DCONn[21:20]), transfer size (DCONn[28]), and initial transfer count, respectively. This value will be loaded into CURR_TC only if the CURR_TC is 0 and the DMA ACK is 1. 0000 0 DMA STATUS REGISTER (DSTAT) Register DSTAT0 DSTAT1 DSTAT2 DSTAT3 Address 0x40400014 0x40500014 0x40600014 0x40700014 R/W R R R R Description DMA0 Count Register DMA1 Count Register DMA2 Count Register DMA3 Count Register Reset Value 000000h 000000h 000000h 000000h DSTATn STAT Bit [21:20] Description Status of this DMA controller. 00: It indicates that DMA controller is ready for another DMA request. 01: It indicates that DMA controller is busy for transfers. Initial State 00b CURR_TC [19:0] Current value of transfer count. Note that transfer count is initially set to the value of DCONn[19:0] register and decreased by one at the end of every atomic transfer. 00000h 9-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 DMA S3C24A0 RISC MICROPROCESSOR DMA CURRENT SOURCE REGISTER (DCSRC) Register DCSRC0 DCSRC1 DCSRC2 DCSRC3 Address 0x40400018 0x40500018 0x40600018 0x40700018 R/W R R R R Description DMA0 Current Source Register DMA1 Current Source Register DMA2 Current Source Register DMA3 Current Source Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DCSRCn CURR_SRC Bit [30:0] Description Current source address for DMAn. Initial State 0x00000000 CURRENT DESTINATION REGISTER (DCDST) Register DCDST0 DCDST1 DCDST2 DCDST3 Address 0x4040001c 0x4050001c 0x4060001c 0x4070001c R/W R R R R Description DMA0 Current Destination Register DMA1 Current Destination Register DMA2 Current Destination Register DMA3 Current Destination Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DCDSTn CURR_DST Bit [30:0] Description Current destination address for DMAn. Initial State 0x00000000 9-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR DMA DMA MASK TRIGGER REGISTER (DMASKTRIG) Register DMASKTRIG0 DMASKTRIG1 DMASKTRIG2 DMASKTRIG3 Address 0x40400020 0x40500020 0x40600020 0x40700020 R/W R/W R/W R/W R/W Description DMA0 Mask Trigger Register DMA1 Mask Trigger Register DMA2 Mask Trigger Register DMA3 Mask Trigger Register Reset Value 000 000 000 000 DMASKTRIGn STOP Bit [2] Stop the DMA operation. Description 1: DMA stops as soon as the current atomic transfer ends. If there is no current running atomic transfer, DMA stops immediately. The CURR_TC, CURR_SRC, CURR_DST will be 0. NOTE: Due to possible current atomic transfer, "stop" may take several cycles. The finish of "stopping" operation (i.e., actual stop time) can be detected by waiting until the channel on/off bit(DMASKTRIGn[1]) is set to off. This stop is "actual stop". Initial State 0 ON_OFF [1] DMA channel on/off bit. 0: DMA channel is turned off. (DMA request to this channel is ignored.) 1: DMA channel is turned on and the DMA request is handled. This bit is automatically set to off if we set the DCONn[22] bit to "no auto reload" and/or STOP bit of DMASKTRIGn to "stop". Note that when DCON[22] bit is "no auto reload", this bit becomes 0 when CURR_TC reaches 0. If the STOP bit is 1, this bit becomes 0 as soon as the current atomic transfer finishes. NOTE. This bit should not be changed manually during DMA operations (i.e., this has to be changed only by using DCON[22] or STOP bit.) 0 SW_TRIG [0] Trigger the DMA channel in S/W request mode. 1: it requests a DMA operation to this controller. 0 However, note that for this trigger to have effects S/W request mode has to be selected (DCONn[23]) and channel ON_OFF bit has to be set to 1 (channel on). When DMA operation starts, this bit is cleared automatically. NOTE. You can freely change the values of DISRC register, DIDST registers, and TC field of DCON register. Those changes take effect only after the finish of current transfer (i.e., when CURR_TC becomes 0). On the other hand, any change made to other registers and/or fields takes immediate effect. Therefore, be careful in changing those registers and fields. 9-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR REAL TIME CLOCK RTC (REAL TIME CLOCK)(Preliminary) OVERVIEW The RTC (Real Time Clock) unit can be operated by the backup battery while the system power is off. The RTC can transmit 8-bit data to CPU as BCD (Binary Coded Decimal) values using the STRB/LDRB ARM operation. The data include second, minute, hour, date, day, month, and year. The RTC unit works with an external 32.768 KHz crystal and also can perform the alarm function. FEATURE -- BCD number : second, minute, hour, date, day, month, year -- Leap year generator -- Alarm function : alarm interrupt or wake-up from power down mode. -- Year 2000 problem is removed. -- Independent power pin (RTCVDD) -- Supports millisecond tick time interrupt for RTOS kernel time tick. -- Round reset function 10-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 REAL TIME CLOCK S3C24A0 RISC MICROPROCESSOR REAL TIME CLOCK OPERATION T CT IN Ti m Ti ck G e ener at or 128 H z 15 Cl ock 2 Di vi der RCS T RT Reset Regi st er TM TC IEIK Leap Year G ener at or X I rtc T 1H z SEC XO T rtc MN I HO UR DATE DAY MN O YEAR Cont r ol Regi st er RCO T CN P WU MK P Al ar m G ener at or RCL T AM PD WN A MN LI T Figure 10-1. Real Time Clock Block Diagram LEAP YEAR GENERATOR This block can determine whether the last date of each month is 28, 29, 30, or 31, based on data from BCDDATE, BCDMON, and BCDYEAR. This block considers the leap year in deciding on the last date. An 8-bit counter can only represent 2 BCD digits, so it cannot decide whether 00 year is a leap year or not. For example, it can not discriminate between 1900 and 2000. To solve this problem, the RTC block in S3C24A0 has hard-wired logic to support the leap year in 2000. Please note 1900 is not leap year while 2000 is leap year. Therefore, two digits of 00 in S3C24A0 denote 2000, not 1900. READ/WRITE REGISTERS Bit 0 of the RTCCON register must be set to high in order to write the BCD register in RTC block. To display the sec., min., hour, date, month, and year, the CPU should read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDAY, BCDDATE, BCDMON, and BCDYEAR registers, respectively, in the RTC block. However, a one second deviation may exist because multiple registers are read. For example, when the user reads the registers from BCDYEAR to BCDMIN, the result is assumed to be 2059(Year), 12(Month), 31(Date), 23(Hour) and 59(Minute). When the user read the BCDSEC register and the result is a value from 1 to 59(Second), there is no problem, but, if the result is 0 sec., the year, month, date, hour, and minute may be changed to 2060(Year), 1(Month), 1(Date), 0(Hour) and 0(Minute) because of the one second deviation that was mentioned. In this case, user should re-read from BCDYEAR to BCDSEC if BCDSEC is zero. BACKUP BATTERY OPERATION The RTC logic can be driven by the backup battery, which supplies the power through the RTCVDD pin into RTC block, even if the system power is off. When the system off, the interfaces of the CPU and RTC logic should be blocked, and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation. 10-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR REAL TIME CLOCK 2003-01-15 ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power down mode or normal operation mode. In normal operation mode, the alarm interrupt (ALMINT) is activated. In the power down mode the power management wakeup (PMWKUP) signal is activated as well as the ALMINT. The RTC alarm register, RTCALM, determines the alarm enable/disable and the condition of the alarm time setting. TICK TIME INTERRUPT The RTC tick time is used for interrupt request. The TICNT register has an interrupt enable bit and the count value for the interrupt. The count value reaches '0' when the tick time interrupt occurs. Then the period of interrupt is as follow: Period = ( n+1 ) / 128 second n : Tick time count value (1~127) This RTC time tick may be used for RTOS(real time operating system) kernel time tick. If time tick is generated by RTC time tick, the time related function of RTOS will always synchronized with real time. ROUND RESET FUNCTION The round reset function can be performed by the RTC round reset register, RTCRST. The round boundary (30, 40, or 50 sec) of the second carry generation can be selected, and the second value is rounded to zero in the round reset. For example, when the current time is 23:37:47 and the round boundary is selected to 40 sec, the round reset changes the current time to 23:38:00. NOTE All RTC registers have to be accessed by the byte unit using the STRB,LDRB instructions or char type pointer. 32.768KHZ X-TAL CONNECTION EXAMPLE The Figure 10-2 is an example circuit of the RTC unit oscillation at 32.768Khz. 15~ 22pF XTIrtc 32768Hz XTOrtc Figure 10-2. Main Oscillator Circuit Examples 10-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 REAL TIME CLOCK S3C24A0 RISC MICROPROCESSOR R E A L T IM E C L O C K S P E C IA L R E G IS T E R S REAL TIME CLOCK CONTROL REGISTER (RTCCON) The RTCCON register consists of 4 bits such as the RTCEN, which controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, so it should be set to 1 in an RTC control routine to enable data read/write after a system reset. Also before power off, the RTCEN bit should be cleared to 0 to prevent inadvertent writing into RTC registers. Register RTCCON Address 0x44200040 R/W R/W (by byte) Description RTC control Register Reset Value 0x0 RTCCON CLKRST CNTSEL Bit [3] [2] RTC clock count reset 0 = No reset, 1 = Reset Description Initial State 0 0 BCD count select 0 = Merge BCD counters 1 = Reserved (Separate BCD counters) BCD clock select 0 = XTAL 1/215 divided clock 1 = Reserved (XTAL clock only for test) RTC control enable 0 = Disable NOTE : Only BCD time count and read operation can be performed. 1 = Enable CLKSEL [1] 0 RTCEN [0] 0 NOTES: 1. All RTC registers have to be accessed by byte unit using STRB and LDRB instructions or char type pointer. TICK TIME COUNT REGISTER (TICNT) Register TICNT Address 0x44200044 R/W R/W (by byte) Description Tick time count Register Reset Value 0x0 TICNT TICK INT ENABLE TICK TIME COUNT Bit [7] [6:0] Description Tick time interrupt enable 0 = Disable 1 = Enable Tick time count value. (1~127) This counter value decreases internally, and users can not read this real counter value in working. Initial State 0 000000 10-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR REAL TIME CLOCK 2003-01-15 RTC ALARM CONTROL REGISTER (RTCALM) RTCALM register determines the alarm enable and the alarm time. Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode, but only through ALMINT in the normal operation mode. Register RTCALM Address 0x44200050 R/W R/W (by byte) Description RTC alarm control Register Reset Value 0x0 RTCALM Reserved ALMEN YEAREN MONREN DATEEN HOUREN MINEN SECEN Bit [7] [6] [5] [4] [3] [2] [1] [0] Reserved Description Alarm global enable 0 = Disable, 1 = Enable Year alarm enable 0 = Disable, 1 = Enable Month alarm enable 0 = Disable, 1 = Enable Date alarm enable 0 = Disable, 1 = Enable Hour alarm enable 0 = Disable, 1 = Enable Minute alarm enable 0 = Disable, 1 = Enable Second alarm enable 0 = Disable, 1 = Enable Initial State 0 0 0 0 0 0 0 0 10-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 REAL TIME CLOCK S3C24A0 RISC MICROPROCESSOR ALARM SECOND DATA REGISTER (ALMSEC) Register ALMSEC Address 0x44200054 R/W R/W (by byte) Description Alarm second data Register Reset Value 0x0 ALMSEC Reserved SECDATA Bit [7] [6:4] [3:0] Reserved Description BCD value for alarm second from 0 to 5 from 0 to 9 Initial State 0 000 0000 ALARM MIN DATA REGISTER (ALMMIN) Register ALMMIN Address 0x44200058 R/W R/W (by byte) Description Alarm minute data Register Reset Value 0x00 ALMMIN Reserved MINDATA Bit [7] [6:4] [3:0] Reserved Description BCD value for alarm minute from 0 to 5 from 0 to 9 Initial State 0 000 0000 ALARM HOUR DATA REGISTER (ALMHOUR) Register ALMHOUR Address 0x4420005C R/W R/W (by byte) Description Alarm hour data Register Reset Value 0x0 ALMHOUR Reserved HOURDATA Bit [7:6] [5:4] [3:0] Reserved Description BCD value for alarm hour from 0 to 2 from 0 to 9 Initial State 00 00 0000 10-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR REAL TIME CLOCK 2003-01-15 ALARM DATE DATA REGISTER (ALMDATE) Register ALMDATE Address 0x44200060 R/W R/W (by byte) Description Alarm date data Register Reset Value 0x01 ALMDATE Reserved DATEDATA Bit [7:6] [5:4] [3:0] Reserved Description BCD value for alarm date, from 0 to 28, 29, 30, 31 from 0 to 3 from 0 to 9 Initial State 00 00 0001 ALARM MON DATA REGISTER (ALMMON) Register ALMMON Address 0x44200064 R/W R/W (by byte) Description Alarm month data Register Reset Value 0x01 ALMMON Reserved MONDATA Bit [7:5] [4] [3:0] Reserved Description BCD value for alarm month from 0 to 1 from 0 to 9 Initial State 00 0 0001 ALARM YEAR DATA REGISTER (ALMYEAR) Register ALMYEAR Address 0x44200068 R/W R/W (by byte) Description Alarm year data Register Reset Value 0x0 ALMYEAR YEARDATA Bit [7:0] BCD value for year from 00 to 99 Description Initial State 0x0 10-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 REAL TIME CLOCK S3C24A0 RISC MICROPROCESSOR RTC ROUND RESET REGISTER (RTCRST) Register RTCRST Address 0x4420006C R/W R/W (by byte) Description RTC round reset Register Reset Value 0x0 RTCRST SRSTEN SECCR Bit [3] [2:0] Description Round second reset enable 0 = Disable, 1 = Enable Round boundary for second carry generation. 011 = over than 30 sec 100 = over than 40 sec 101 = over than 50 sec NOTE : If other values(0,1,2,6,7) are set, no second carry is generated. But second value can be reset. Initial State 0 000 BCD SECOND REGISTER (BCDSEC) Register BCDSEC Address 0x44200070 R/W R/W (by byte) Description BCD second Register Reset Value Undefined BCDSEC SECDATA Bit [6:4] [3:0] BCD value for second from 0 to 5 from 0 to 9 Description Initial State - BCD MINUTE REGISTER (BCDMIN) Register BCDMIN Address 0x44200074 R/W R/W (by byte) Description BCD minute Register Reset Value Undefined BCDMIN MINDATA Bit [6:4] [3:0] BCD value for minute from 0 to 5 from 0 to 9 Description Initial State - 10-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR REAL TIME CLOCK 2003-01-15 BCD HOUR REGISTER (BCDHOUR) Register BCDHOUR Address 0x44200078 R/W R/W (by byte) Description BCD hour Register Reset Value Undefined BCDHOUR Reserved HOURDATA Bit [7:6] [5:4] [3:0] Reserved Description BCD value for hour from 0 to 2 from 0 to 9 Initial State - BCD DATE REGISTER (BCDDATE) Register BCDDATE Address 0x4420007C R/W R/W (by byte) Description BCD date Register Reset Value Undefined BCDDATE Reserved DATEDATA Bit [7:6] [5:4] [3:0] Reserved BCD value for date from 0 to 3 from 0 to 9 Description Initial State - BCD DAY REGISTER (BCDDAY) Register BCDDAY Address 0x44200080 R/W R/W (by byte) Description BCD day Register Reset Value Undefined BCDDAY Reserved DAYDATA Bit [7:3] [2:0] Reserved BCD value for day from 1 to 7 Description Initial State - 10-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 REAL TIME CLOCK S3C24A0 RISC MICROPROCESSOR BCD MONTH REGISTER (BCDMON) Register BCDMON Address 0x44200084 R/W R/W (by byte) Description BCD month Register Reset Value Undefined BCDMON Reserved MONDATA Bit [7:5] [4] [3:0] Reserved Description BCD value for month from 0 to 1 from 0 to 9 Initial State - BCD YEAR REGISTER (BCDYEAR) Register BCDYEAR Address 0x44200088 R/W R/W (by byte) Description BCD year Register Reset Value Undefined BCDYEAR YEARDATA Bit [7:0] BCD value for year from 00 to 99 Description Initial State - 10-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR UART UART(Preliminary) OVERVIEW The S3C24A0 UART (Universal Asynchronous Receiver and Transmitter) unit provides two independent asynchronous serial I/O (SIO) ports, each of which can operate in interrupt-based or DMA-based mode. In other words, UART can generate an interrupt or DMA request to transfer data between CPU and UART. It can support bit rates of up to 115.2K bps, when UART use system clock. If external device provides UART with UCLK, then UART can operates at more higher speed. Each UART channel contains two 64-byte FIFOs for receiver and transmitter. The S3C24A0 UART includes programmable baud-rates, infrared (IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking. Each UART contains a baud-rate generator, transmitter, receiver and control unit, as shown in Figure11-1. The baud-rate generator can be clocked by PCLK. The transmitter and the receiver contain 64-byte FIFOs and data shifters. Data, which is to be transmitted, is written to FIFO and then copied to the transmit shifter. It is then shifted out by the transmit data pin (TxDn). The received data is shifted from the receive data pin (RxDn), and then copied to FIFO from the shifter. FEATURES -- RxD0, TxD0, RxD1, TxD1 with DMA-based or interrupt-based operation -- UART Ch 0, 1 with IrDA 1.0 & 64-byte FIFO -- UART Ch 0, 1 with nRTS0, nCTS0, nRTS1, nCTS1 -- Supports handshake transmit / receive 11-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 UART S3C24A0 RISC MICROPROCESSOR BLOCK DIAGRAM Peripheral BUS Transmitter Transmit FIFO Register (FIFO mode) Transmit Buffer Register(64 Byte) Transmit Holding Register (Non-FIFO mode) Transmit Shifter TXDn Control Unit Receiver Buad-rate Generator Clock Source Receive Shifter RXDn Receive Buffer Register(64 Byte) Receive Holding Register (Non-FIFO mode only) Receive FIFO Register (FIFO mode) In FIFO mode, all 64 Byte of Buffer register are used as FIFO register. In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register. Figure 11-1. UART Block Diagram (with FIFO) 11-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR UART UART OPERATION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, loopback mode, infrared mode, and auto flow control. Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn). The transmitter can also produce the break condition. The break condition forces the serial output to logic 0 state for one frame transmission time. This block transmits break signal after the present transmission word transmits perfectly. After the break signal transmission, it continously transmits data into the Tx FIFO (Tx holding register in the case of Non-FIFO mode). Data Reception Like the transmission, the data frame for reception is also programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits in the line control register (ULCONn). The receiver can detect overrun error. The overrun error indicates that new data has overwritten the old data before the old data has been read. Receive time-out condition occurs when it does not receive data during the 3 word time (This interval follows the setting of Word Length bit) and the Rx FIFO is not empty in the FIFO mode. Auto Flow Control(AFC) S3C24A0's UART 0 and UART 1 support auto flow control with nRTS and nCTS signals, in case, it would have to connect UART to UART. If users connect UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software. In AFC, nRTS is controlled by condition of the receiver and operation of transmitter is controlled by the nCTS signal. The UART's transmitter transfers the data in FIFO only when nCTS signal active (In AFC, nCTS means that the other UART's FIFO is ready to receive data). Before the UART receives data, nRTS has to be activated when its receive FIFO has a spare more than 32-byte and has to be inactivated when its receive FIFO has a spare under 32-byte (In AFC, nRTS means that its own receive FIFO is ready to receive data). Transmission case in UART A UART A TxD nCTS UART B RxD nRTS Reception case in UART A UART A RxD nRTS UART B TxD nCTS Figure 11-2. UART AFC interface 11-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 UART S3C24A0 RISC MICROPROCESSOR Non Auto-Flow control (Controlling nRTS and nCTS by S/W) Example Rx operation with FIFO 1. Select receive mode(Interrupt or DMA mode) 2. Check the value of Rx FIFO count in UFSTATn register. If the value is less than 32, users have to set the value of UMCONn[0] to '1'(activate nRTS), and if it is equal or larger than 32, users have to set the value to '0'(inactivate nRTS). 3. Repeat step 2. Tx operation with FIFO 1. Select transmit mode (Interrupt or DMA mode) 2. Check the value of UMSTATn[0]. If the value is '1'(nCTS is activated), users write the data to Tx FIFO register. 11-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR UART RS-232C interface If users connect to modem interface (not equal null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals are need. In this case, users control these signals with general I/O ports by S/W because the AFC does not support the RS-232C interface. Interrupt/DMA Request Generation Each UART of S3C24A0 has four status (Tx/Rx/Error) signals: Overrun error, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty, all of which are indicated by the corresponding UART status register (UTRSTATn/UERSTATn). The overrun error can cause the receive error status interrupt request, if the receive-error-status-interrupt-enable bit is set to one in the control register, UCONn. When the receiver transfers the data of the receive shifter to the receive FIFO register in FIFO mode and the number of received data reaches Rx FIFO Trigger Level, Rx interrupt is generated, if Receive mode in control register(UCONn) is selected as 1(Interrupt request or polling mode). In the Non-FIFO mode, transfering the data of the receive shifter to the receive holding register will cause Rx interrupt under the Interrupt request and polling mode. When the transmitter transfers data from its transmit FIFO register to its transmit shifter and the number of data left in transmit FIFO reaches Tx FIFO Trigger Level, Tx interrupt is generated, if Transmit mode in control register is selected as Interrupt request or polling mode. In the Non-FIFO mode, transfering data from the transmit holding register to the transmit shifter will cause Tx interrupt under the Interrupt request and polling mode. If the Receive mode and Transmit mode in control register are selected as the DMAn request mode then DMAn request is occurred instead of Rx or Tx interrupt in the situation mentioned above. Table 11-1. Interrupts in Connection with FIFO Type Rx interrupt FIFO Mode Each time receive data reaches the trigger level of receive FIFO, the Rx interrupt will be generated. When the number of data in FIFO does not reaches Rx FIFO trigger Level and does not receive data during 3 word time(This interval follows the setting of Word Length bit), the Rx interrupt will be generated(receive time out). Tx interrupt Non-FIFO Mode Each time receive data becomes full, the receive holding register generates an interrupt. Each time transmit data reaches the trigger level of Each time transmit data become empty, transmit FIFO(Tx FIFO trigger Level), the Tx the transmit holding register generates interrupt will be generated. an interrupt. Overrun error will be generated, when it gets to the Overrun error generates an error top of the receive FIFO without reading out data in interrupt immediately. it. Error interrupt 11-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 UART S3C24A0 RISC MICROPROCESSOR UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out. To clear the error status FIFO, the URXHn with an error and UERSTATn must be read out. For example, It is assumed that the UART Rx FIFO receives A, B, C, D,and E characters sequentially and the frame error occurs while receiving 'B', and the parity error occurs while receiving 'D'. The actual UART receive error will not generate any error interrupt because the character, which was received with an error, has not been read yet. The error interrupt will occur when the character is read out. Figure 11-3 shows the UART receiving the five characters including the two errors. Time #0 #1 #2 #3 #4 #5 #6 Sequence Flow When no character is read out A, B, C, D, and E is received After A is read out After B is read out After C is read out After D is read out After E is read out Error Interrupt The frame error (in B) interrupt occurs. The parity error (in D) interrupt occurs. The 'D' has to be read out. The 'B' has to be read out. Note Rx FIFO 'E' 'D' 'C' 'B' 'A' URXHn UERSTATn Error Status FIFO break error parity error frame error Error Status Generator Unit Figure 11-3. Example showing UART Receiving 5 Characters with 2 Errors 11-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR UART Baud-Rate Generation Each UART's baud-rate generator provides the serial clock for transmitter and receiver. The source clock for the baud-rate generator can be selected with the S3C24A0's internal system clock or UCLK. In other words, dividend can be selected by the setting of Clock Selection of UCONn. The baud-rate clock is generated by dividing the source clock(PCLK or UCLK) by 16 and a 16-bit divisor specified in the UART baud-rate divisor register (UBRDIVn). The UBRDIVn can be determined as follows: UBRDIVn = (int)(PCLK/(bps x 16) ) -1 where the UBRDIVn should be from 1 to (216-1). For the accurate UART operation, S3C24A0 also supports UARTCLK as a dividend. If UARTCLK, supplied by external UART device or system, is used, then serial clock of UART is exactly synchronized with UARTCLK. So, user can get the more precision UART operation. The UBRDIVn can be determined as follows: UBRDIVn = (int)( UARTCLK / (bps x 16) ) -1 where the UBRDIVn should be from 1 to (216-1) and UARTCLK should be smaller than PCLK. For example, if the baud-rate is 115200 bps and PCLK or UARTCLK is 40 MHz , UBRDIVn is: UBRDIVn = (int)(40000000/(115200 x 16) ) -1 = (int)(21.7) -1 = 22 -1 = 21 Baud-Rate Error Tolerance UART Frame error should be less than 1.87%(3/160). tUPCLK = (UBRDIVn + 1) x 16 x 10 / PCLK tUEXACT = 10 / baud-rate tUPCLK : Real UART clock time tUEXACT : Ideal UART clock time UART error = (tUPCLK - tUEXACT) / tUEXACT x 100% NOTE. 1. 1Frame = 1start bit + 8 data bit + 1 stop bit. 2. In specific condition, we can support bit rates up to 921.6K bps. For example, when PCLK is 60MHz, you can use bit rates of 921.6K bps under UART error of 1.69%. Loop-back Mode The S3C24A0 UART provides a test mode referred to as the loopback mode, to aid in isolating faults in the communication link. In this mode, the transmitted data is immediately received. This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel. This mode can be selected by setting the loopback-bit in the UART control register (UCONn). Break Condition The break is defined as a continuous low level signal for one frame transmission time on the transmit data output. 11-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 UART S3C24A0 RISC MICROPROCESSOR IR (Infrared) Mode The S3C24A0 UART block supports infrared (IR) transmission and reception, which can be selected by setting the infrared-mode bit in the UART line control register (ULCONn). The implementation of the mode is shown in Figure 11-3. In IR transmit mode, the transmit period is pulsed at a rate of 3/16, the normal serial transmit rate (when the transmit data bit is zero); In IR receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value (refer to the frame timing diagrams shown in Figure 11-5 and 11-6 ). TxD 0 TxD 1 IRS UART Block RxD 1 RE IrDA Tx Encoder IrDA Rx Decoder 0 RxD Figure 11-3. IrDA Function Block Diagram 11-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR UART SIO Frame Start Bit Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Figure 11-4. Serial I/O Frame Timing Diagram (Normal UART) IR Transmit Frame Start Bit Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Bit Time Pulse Width = 3/16 Bit Frame Figure 11-5. Infrared Transmit Mode Frame Timing Diagram IR Receive Frame Start Bit Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Figure 11-6. Infrared Receive Mode Frame Timing Diagram 11-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 UART S3C24A0 RISC MICROPROCESSOR UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are two UART line control registers, ULCON0 and ULCON1 in the UART block. Register ULCON0 ULCON1 Address 0x44400000 0x44404000 R/W R/W R/W Description UART channel 0 line control register UART channel 1 line control register Reset Value 0x00 0x00 ULCONn Reserved Infrared Mode Bit [7] [6] Description The Infrared mode determines whether or not to use the Infrared mode. 0 = Normal mode operation 1 = Infrared Tx/Rx mode Initial State 0 0 Parity Mode [5:3] The parity mode specifies how parity generation and checking are to be performed during UART transmit and receive operation. 0xx = No parity 100 = Odd parity 101 = Even parity 110 = Parity forced/checked as 1 111 = Parity forced/checked as 0 000 Number of stop bit [2] The number of stop bits specifies how many stop bits are to be used to signal end-of-frame. 0 = One stop bit per frame 1 = Two stop bit per frame 0 Word length [1:0] The word length indicates the number of data bits to be transmitted or received per frame. 00 = 5-bits 10 = 7-bits 01 = 6-bits 11 = 8-bits 00 11-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR UART UART CONTROL REGISTER There are two UART control registers, UCON0 and UCON1 in the UART block. Register UCON0 UCON1 Address 0x44400004 0x44404004 R/W R/W R/W Description UART channel 0 control register UART channel 1 control register Reset Value 0x00 0x00 UCONn Clock selection Bit Description 0=PCLK : UBRDIVn = (int)(PCLK / (bps x 16) ) -1 1= UARTCLK : UBRDIVn = (int)( UARTCLK / (bps x 16) ) -1 Initial State 0 [10] Select PCLK or UARTCLK for the UART baud rate. Tx interrupt type [9] Interrupt request type 0 = Pulse (Interrupt is requested as soon as the Tx buffer becomes empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode) 1 = Level (Interrupt is requested while Tx buffer is empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode) 0 Rx interrupt type [8] Interrupt request type 0 = Pulse (Interrupt is requested the instant Rx buffer receives the data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode) 1 = Level (Interrupt is requested while Rx buffer is receiving data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode) 0 Rx time out enable Rx error status interrupt enable [7] Enable/Disable Rx time out interrupt when UART FIFO is enabled. The interrupt is a receive interrupt. 0 = Disable 1 = Enable This bit enables the UART to generate an interrupt if overrun error occurs during a receive operation. 0 = Do not generate receive error status interrupt 1 = Generate receive error status interrupt 0 [6] 0 Loop-back Mode [5] Setting loop-back bit to 1 causes the UART to enter the loop-back mode. This mode is provided for test purposes only. 0 = Normal operation 1 = Loop-back mode Setting this bit causes the UART to send a break during 1 frame time. This bit is auto-cleared after sending the break signal. 0 = Normal transmit 1 = Send break signal 0 Send Break Signal [4] 0 11-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 UART S3C24A0 RISC MICROPROCESSOR UART CONTROL REGISTER (CONTINUED) Transmit Mode [3:2] These two bits determine which function is currently able to write Tx data to the UART transmit buffer register. 00 = Disable 01 = Interrupt request or polling mode 10 = DMA0 or DMA2 request (Only for UART0), 11 = DMA1 or DMA3 request (Only for UART1) Receive Mode [1:0] These two bits determine which function is currently able to read data from UART receive buffer register. 00 = Disable 01 = Interrupt request or polling mode 10 = DMA0 or DMA2 request (Only for UART0), 11 = DMA1 or DMA3 request (Only for UART1) Note : When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status and read out the rest. 00 00 11-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR UART UART FIFO CONTROL REGISTER There are two UART FIFO control registers, UFCON0 and UFCON1 in the UART block. Register UFCON0 UFCON1 Address 0x44400008 0x44404008 R/W R/W R/W Description UART channel 0 FIFO control register UART channel 1 FIFO control register Reset Value 0x0 0x0 UFCONn Tx FIFO Trigger Level Bit [7:6] Description These two bits determine the trigger level of transmit FIFO. 00 = Empty 01 = 16-byte 10 = 32-byte 11 = 48-byte These two bits determine the trigger level of receive FIFO. 00 = 1-byte 01 = 8-byte 10 = 16-byte 11 = 32-byte This bit is auto-cleared after resetting FIFO 0 = Normal 1= Tx FIFO reset This bit is auto-cleared after resetting FIFO 0 = Normal 1= Rx FIFO reset 0 = FIFO disable 1 = FIFO mode Initial State 00 Rx FIFO Trigger Level [5:4] 00 Reserved Tx FIFO Reset Rx FIFO Reset FIFO Enable [3] [2] [1] [0] 0 0 0 0 Note : When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO, the Rx interrupt will be generated(receive time out), and the users should check the FIFO status and read out the rest. 11-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 UART S3C24A0 RISC MICROPROCESSOR UART MODEM CONTROL REGISTER There are two UART MODEM control registers, UMCON0 and UMCON1, in the UART block. Register UMCON0 UMCON1 Address 0x4440000C 0x4440400C R/W R/W R/W Description UART channel 0 Modem control register UART channel 1 Modem control register Reset Value 0x0 0x0 UMCONn Reserved AFC(Auto Flow Control) Reserved Request to Send Bit [7:5] [4] [3:1] [0] These bits must be 0's 0 = Disable These bits must be 0's Description 1 = Enable Initial State 00 0 00 0 If AFC bit is enabled, this value will be ignored. In this case the S3C24A0 will control nRTS automatically. If AFC bit is disabled, nRTS must be controlled by S/W. 0 = 'H' level(Inactivate nRTS) 1 = 'L' level(Activate nRTS) 11-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR UART UART TX/RX STATUS REGISTER There are two UART Tx/Rx status registers, UTRSTAT0 and UTRSTAT1 in the UART block. Register UTRSTAT0 UTRSTAT1 Address 0x44400010 0x44404010 R/W R R Description UART channel 0 Tx/Rx status register UART channel 1 Tx/Rx status register Reset Value 0x6 0x6 UTRSTATn Transmitter empty Bit [2] Description This bit is automatically set to 1 when the transmit buffer register has no valid data to transmit and the transmit shift register is empty. 0 = Not empty 1 = Transmitter(transmit buffer & shifter register) empty This bit is automatically set to 1 when transmit buffer register is empty. 0 =The buffer register is not empty 1 = Empty (In Non-FIFO mode, Interrupt or DMA is requested. In FIFO mode, Interrupt or DMA is requested, when Tx FIFO Trigger Level is set to 00(Empty)) If the UART uses the FIFO, users should check Tx FIFO Count bits and Tx FIFO Full bit in the UFSTAT register instead of this bit. Initial State 1 Transmit buffer empty [1] 1 Receive buffer data ready [0] This bit is automatically set to 1 whenever receive buffer register contains valid data, received over the RXDn port. 0 = Empty 1 = The buffer register has a received data (In Non-FIFO mode, Interrupt or DMA is requested) If the UART uses the FIFO, users should check Rx FIFO Count bits and Rx FIFO Full bit in the UFSTAT register instead of this bit. 0 11-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 UART S3C24A0 RISC MICROPROCESSOR UART ERROR STATUS REGISTER There are two UART Rx error status registers, UERSTAT0 and UERSTAT1 in the UART block. Register UERSTAT0 UERSTAT1 Address 0x44400014 0x44404014 R/W R R Description UART channel 0 Rx error status register UART channel 1 Rx error status register Reset Value 0x0 0x0 UERSTATn Overrun Error Bit [0] Description This bit is automatically set to 1 whenever an overrun error occurs during receive operation. 0 = No overrun error during receive 1 = Overrun error(Interrupt is requested) Initial State 0 NOTE : This bit is automatically cleared to 0 when the UART error status register is read. 11-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR UART UART FIFO STATUS REGISTER There are two UART FIFO status registers, UFSTAT0 and UFSTAT1 in the UART block. Register UFSTAT0 UFSTAT1 Address 0x44400018 0x44404018 R/W R R Description UART channel 0 FIFO status register UART channel 1 FIFO status register Reset Value 0x0000 0x0000 UFSTATn Reserved Tx FIFO Full Bit [15] [14] Description This bit is automatically set to 1 whenever transmit FIFO is full during transmit operation 0 = 0-byte Tx FIFO data 63-byte 1 = Full Number of data in Tx FIFO This bit is automatically set to 1 whenever receive FIFO is full during receive operation 0 = 0-byte Rx FIFO data 63-byte 1 = Full Number of data in Rx FIFO Initial State 0 0 Tx FIFO Count Reserved Rx FIFO Full [13:8] [7] [6] 0 0 0 Rx FIFO Count [5:0] 0 11-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 UART S3C24A0 RISC MICROPROCESSOR UART MODEM STATUS REGISTER There are two UART modem status registers, UMSTAT0 and UMSTAT1 in the UART block. Register UMSTAT0 UMSTAT1 Address 0x4440001C 0x4440401C R/W R R Description UART channel 0 Modem status register UART channel 1 Modem status register Reset Value 0x00 0x00 UMSTAT0 Reserved DCTS Bit [7:5] [4] Delta CTS Description Initial State 0 0 This bit indicates that the nCTS input to S3C24A0 has changed state since the last time it was read by CPU. (Refer to Figure 11-7) 0 = Has not changed 1 = Has changed Reserved Clear to Send [3:1] [0] 0 = CTS signal is not activated(nCTS pin is high) 1 = CTS signal is activated(nCTS pin is low) 0 0 nCTS DCTS Read_UMSTAT Figure 11-7. nCTS and Delta CTS Timing Diagram 11-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR UART UART TRANSMIT BUFFER REGISTER(HOLDING REGISTER & FIFO REGISTER) There are two UART transmit buffer registers, UTXH0 and UTXH1 in the UART block. UTXHn has an 8-bit data for transmission data. Register UTXH0 UTXH1 Address 0x44400020 0x44404020 R/W Description Reset Value - W UART channel 0 transmit buffer register (by byte) W UART channel 1 transmit buffer register (by byte) UTXHn TXDATAn Bit [7:0] Description Transmit data for UARTn Initial State - UART RECEIVE BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are two UART receive buffer registers, URXH0 and URXH1 in the UART block. URXHn has an 8-bit data for received data. Register URXH0 URXH1 Address 0x44400024 0x44404024 R/W Description Reset Value - R UART channel 0 receive buffer register (by byte) R UART channel 1 receive buffer register (by byte) URXHn RXDATAn Bit [7:0] Description Receive data for UARTn Initial State - NOTE: When an overrun error occurs, the URXHn must be read. If not, the next received data will also make an overrun error, even though the overrun bit of UERSTATn had been cleared. 11-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 UART S3C24A0 RISC MICROPROCESSOR UART BAUD RATE DIVISOR REGISTER There are two UART baud rate divisor registers, UBRDIV0 and UBRDIV1 in the UART block. The value stored in the baud rate divisor register (UBRDIVn), is used to determine the serial Tx/Rx clock rate (baud rate) as follows: UBRDIVn or UBRDIVn = (int)( UARTCLK / (bps x 16) ) -1 = (int)(PCLK / (bps x 16) ) -1 where the UBRDIVn should be from 1 to (216-1) and UARTCLK should be smaller than PCLK. For example, if the baud-rate is 115200 bps and PCLK or UARTCLK is 40 MHz , UBRDIVn is: UBRDIVn = (int)(40000000 / (115200 x 16) ) -1 = (int)(21.7) -1 = 22 -1 = 21 Register UBRDIV0 UBRDIV1 Address 0x44400028 0x44404028 R/W R/W R/W Description Baud rate divisior register 0 Baud rate divisior register 1 Reset Value - UBRDIV n UBRDIV Bit [15:0] Description Baud rate division value UBRDIVn >0(if UARTCLK is used, UBRDIVn>=0) Initial State - 11-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IRDA CONTROLLER IRDA CONTROLLER(Preliminary) OVERVIEW The Samsung IrDA Core is a wireless serial communication controller. Supporting two different types of IrDA speed(MIR, FIR), this core can transmit Ir(Infrared) pulses up to 4 Mbps speed. To lessen the CPU burden, it has configurable FIFO feature. This makes it easy to adjust the internal FIFO sizes. A user can program the core by accessing 16 internal registers. When receiving the Ir pulses, this core detects three kinds of line errors such as CRC-error, PHY-error and payload length error. FEATURE 1. IrDA specification compliant - support IrDA 1.1 physical layer specification (4Mbps, 1.152Mpbs and 0.576Mbps) 2. Supports FIFO operation in the MIR and FIR mode 3. Configurable FIFO size (16-byte or 64-byte) 4. Supports Back-to-Back Transactions 5. Supports software in selecting Temic-IBM or HP transceiver 12-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IRDA CONTROLLER S3C24A0 RISC MICROPROCESSOR BLOCK DIAGRAM INTERRUPT, DMA MASTER_Control Iinterrupt Control and payload length store IER ICR RXFLH RXFLL TXFLH TXFLL MCLK(48MHz) HRESETn CLK_GEN LSR ACREG MDR FCR IRSDBW AHB BUS TX FIFO Control TX FIFO RAM THR PLR FIR Mod/Demodl PLL IRRX MOD DEMOD RX FIFO Control RX FIFO RAM RBR M MIR Mod/Demodl MOD DEMOD MUX IRTX Figure 12-1. Block Diagram EXTERNAL INTERFACE SIGNALS IrDA_Tx IrDA_Rx IrDA_SDBW : IrDA Tx signal (output) : IrDA Rx signal (input) : IrDA Transceiver control (Shutdown, Bandwidth) (output) 12-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IRDA CONTROLLER FUNCTION DESCRIPTION Fast-Speed Infrared (FIR) Mode (IrDA 1.1) In this FIR mode, data communicates at the baud rate speed of 4 Mbps. In the data transmission mode, the core encodes the payload data into the 4PPM format and attaches the Preamble, Start Flag, CRC-32, and Stop flag on the encoded payload and shifts them out serially. In data receive mode, the core works in reverse direction. First, when Ir pulse is detected, the core recovers receiver clock from the incoming data and removes the Preamble and Start Flag, then it extracts the payload from the received 4PPM data until it meets the Stop Flag. The core detects three different kinds of errors which may occur in the middle of transmission. These are the Phy-Error, the Frame-Length Error and the CRC error. The last one, CRC error is checked when the entire payload data is received. The micro-controller can monitor the error status of the received frame by reading the Line Status Register(LSR) at the end of the frame receiving. The below diagram shows the frame structure of the fir data frame. (The specific information of the each field can be found in IrDA specification.) Preamble Start flag Link layer frame(Payload) CRC32 Stop flag Preamble : 1000, 0000, 1010, 1000 Start Flag : 0000, 1100, 0000, 1100, 0110, 0000, 0110,0000 Stop Flag : 0000,1100, 0000, 1100, 0000, 0110, 0000, 0110 By programming the internal registers, the number of preambles can be selected from 4 to 32. * Note : 4 PPM Coding Data Bit Pair(DBP) 00 01 10 11 4PPM Data Symbol(DD) 1000 0100 0010 0001 12-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IRDA CONTROLLER S3C24A0 RISC MICROPROCESSOR TX Enable 0 ena ~ena Preamble Transmit 1 pre_end Start Flag Transmit 2 str_end Pay Load Transmit & CRC apeend Frame data with error crc 6 pay_end abort by underrun ~abort 3 CRC Transmit 4 crc_end Stop Flag Transmit 5 2u Pulse transmit 7 sip stp_end & ena pul_end & ena stp_end & ~ena pul_end & ~ena Figure 12-2. Fir modulation process Figure 12-2 shows the FIR modulation state machine. The FIR transmission mode can be selected by programming ACR register. If an underrun condition occurs, the state machine appends the payload with error crc data and terminate the transmission. 12-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IRDA CONTROLLER ~(ena & prebyte) Rx Enable 0 ena & prebyte Preamble & start flag Detect 1 str_end Pay Load Detect & 4ppm decod 2 phy_err crc_decod_start Pay Load Detect & CRC check 3 pay_end = last_byte CRC Decoding for syndrom 4 stp_start Stop Flag Detect 5 stp_end & ena stp_end & ~ena Figure 12-3. Fir demodulation process Figure 12-3 shows FIR demodulation state machine. The state machine starts when ACR register bit 6 is set to logic high. The incoming data will be depacketized by removing preamble and start flag and stop flag . Also, 4PPM decoding and CRC decoding is carried out. 12-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IRDA CONTROLLER S3C24A0 RISC MICROPROCESSOR Medium-Speed Infrared (MIR) Mode (IrDA 1.1) In MIR mode, data communicates at the speed of 1.152Mbps, and 0.576Mbps(half mode). The payload data is wrapped around by Start Flags, CRC-16, and Stop Flags. The Start Flag should be at least two bytes. Both in transmitting and receiving process, the basic wrapping and de-wrapping processes are same as the FIR mode, but, the MIR mode needs the bit-stuffing procedure. Bit stuffing in MIR mode have the core insert zero bit per every 5 consecutive ones in transmission mode. In receiving mode, the stuffed bit should be removed. Like the fir mode case, three different kind of errors (crc, phy and frame length error ) can be reported to the microcontroller in receiving mode by reading the LSR register. The diagram below shows the data structure of MIR frame. STA STA Link layer frame (Payload) CRC16 STO STA : Beginning flag, 01111110 binary CRC16 : CCITT 16 bit CRC STO : Ending flag, 01111110 binary The MIR pulse is modulated by 1/4 pulse format. The below diagram shows how the pulse is generated. 1.152M NRZ Data MIR Pulse Figure 12-4. Pulse modulation in MIR mode 12-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IRDA CONTROLLER TX Enable ACREG[7] 0 ena ~ena 1st Start Flag Transmit 1 str_end append Frame data with error crc & eflag 6 Pay Load Transmit with stuff bit 2 abort by underrun ~abort pay_end CRC Transmit with stuff bit 3 crc_end Stop Flag Transmit 2u Pulse transmit 5 sip 4 stp_end & ena pul_end & ena stp_end & ~ena pul_end & ~ena Figure 12-5. Mir modulation process. Figure 12-5 shows MIR modulation state machine. This machine works very similarly with FIR modulation state machine. The major difference is that the MIR data transmission needs bit stuffing. After the every 5 consecutive ones, a zero data should be stuffed in MIR payload data. The state machine for this bit-stuffing is not presented here. 12-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IRDA CONTROLLER S3C24A0 RISC MICROPROCESSOR ~(ena&flagbyte) Rx Enable 0 ena & flagbyte Str Flag Detect 1 str_end Pay Load Detect & De-Stuff 2 pay_end CRC check & Stp Det 3 stp_end Figure 12-6 mir demodulation process Figure 12-6 shows the MIR demodulation state machine. Basically, it has similar structure with FIR demodulation state machine. But, instead having 4 PPM demodulation phase, it has the stage of removing stuffed bits from payload data stream. Since the MIR data stream doesn't have preamble data, the preamble/start flag data detection stage in MIR demodulation is simplified to start flag detection state. 12-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IRDA CONTROLLER CORE INITIALIZATION PROCEDURE MIR/FIR Mode Initialization Operation 1) 2) Program the MDR register to select the MIR/FIR mode. Program the ACR register to select the transceiver type. - For the Temic-IBM type transceiver, program twice in ACR[0] = 1'b0 and ACR[0] = 1'b1. - For the HP type transceiver, program just once in ACR[0] = 1'b0 to FIR/MIR mode. 3) 4) 5) 6) 7) 8) 9) Program the PLR register to select the number of preamble or start flag, and TX threshold level. Program the RXFLL and RXFLH register (maximum available receive bytes in frame). Program the TXFLL and TXFLH register (transmit bytes in transmission frame). Program the FCR register (FIFO size and RX threshold level). Program the IER register ( the types of interrupt). Program the ACR register (TX enable or RX enable). Program the ICR register (interrupt enable). 10) Service Interrupt signal from the core. START Setup INT Service Parameters Initialize Core Enable INT No INT Active ? Yes ISR Figure 12-8 General Program Flowchart 12-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IRDA CONTROLLER S3C24A0 RISC MICROPROCESSOR SPECIAL FUNCTION REGISTERS IrDA CONTROL REGISTER(IrDA_CNT) Register Address IrDA _CNT 0x41800000 R/W R/W IrDA Control Register Description Reset Value 0x00 IrDA _CNT TX enable Bit [7] Description TX enable. Bit 7 must be set to `1' to enable data transmission in MIR/FIR Ir modes. RX enable. Bit 6 must be set to `1' to enable data receive in all MIR/FIR Ir modes. Core loop for software debugging. The IRRX port connects directly to the IRTX internally. MIR half mode. When bit 4 is set to a `1', the operating speed in the MIR mode changes from 1.152 Mbps to 0.576 Mbps. Send 1.6-us IR pulse. When the IrDA_MDR[3] bit equals to a `1' and the CPU writes a `1' to this bit, the transmitting interface device sends a 1.6-us IR pulse at the end of the frame. Bit 3 is cleared automatically by the transmitting interface device at the end of 1.6-us IR pulse data transmission. Reserved Frame abort. The CPU can intentionally abort data transmission of a frame by writing a `1' to bit 1. Neither the end flag nor the CRC bits are appended to the frame. The receiver will find the frame with the abort pattern in the MIR mode and a PHY-error in the FIR mode. The CPU must reset the TX FIFO and reset this bit by writing a `0' to bit `1' before next frame can be transmitted. This signal controls IrDA_SDBW output signal. It is used for controlling mode (shutdown, band width) of IrDA transceiver. Initial State 0 RX enable Core loop MIR half mode [6] [5] [4] 0 0 0 Send IR pulse [3] 0 Reserved Frame abort [2] [1] 0 0 SD/BW [0] 0 12-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IRDA CONTROLLER IrDA MODE DEFINITION REGISTER(IrDA_MDR) Register Address IrDA_MDR 0x41800004 R/W R/W Description IrDA Mode Definition Register Reset Value 0x00 IrDA _MDR Reserved SIP Select Bit [7:5] [4] Reserved Description Initial State 0 0 SIP select method. If this bit is set to `1' and the IrDA_CNT[3] is set to `1', the SIP pulse is appended at the end of FIR/MIR TX frame. Likewise, when this bit is set to a `0', SIP is generated at the end of the every FIR/MIR frames. If IrDA_CNT[3] is set to `0', setting this bit to `1' doesn't help to generate SIP. Along with IrDA_CNT[3] bit, the way of SIP generation can be controlled. Bit 3 is Temic transceiver select bit. When bit 3 is clear to "0", core automatically selects in Temic transceiver mode. Bit 2, bit 1 and bit 0 select the mode of operation as 100 : FIR Mode 010 : MIR Mode Temic select Mode select [3] [2:0] 0 0 IrDA INTERRUPT / DMA CONFIGURATION REGISTER(IrDA_CNF) Register IrDA_CNF Address 0x41800008 R/W R/W Description IrDA Interrupt / DMA Configuration Register Reset Value 0x00 IrDA _CNF Reserved DMA Enable DMA Mode Reserved Interrupt Enable Bit [7:4] [3] [2] [1] [0] Reserved 1 : DMA Enable 0 : Tx DMA Reserved Description Initial State 0 1 : Rx DMA 0 0 The bit 0 enables Interrupt output signal. 12-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IRDA CONTROLLER S3C24A0 RISC MICROPROCESSOR IrDA INTERUPT ENALBLE REGISTER(IrDA_IER) Register IrDA _IER Address 0x4180000C R/W R/W Description IrDA Interrupt Enable Register Reset Value 0x00 IrDA_IER Last byte to Rx FIFO Bit [7] Description Enables state indication interrupt when Last byte write to RX FIFO. Enables error status indication interrupt in data receiving mode. Enables transmitter under-run interrupt. Detect stop-flag interrupt enable. If this bit is set to "1", an interrupt signal will be activated when the last byte of the received data frame comes into the demodulation block and the CRC decoding is finished. Enables receiver over-run interrupt. Bit 2 enables last byte from RX FIFO interrupt which is generated when the microcontroller reads the last byte of the frame from the RX FIFO. Bit 1 enables an TX FIFO below threshold level interrupt when the available empty space in TX FIFO is over the threshold level. Bit 0 enables received data in RX FIFO over threshold level interrupt when the RX FIFO is equal to or above the threshold level. Initial State 0 Error indication Tx Underrun Last byte detect [6] [5] [4] 0 0 0 Rx overrun Last byte read from Rx FIFO Tx FIFO below threshold Rx FIFO over threshold [3] [2] 0 0 [1] 0 [0] 0 12-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IRDA CONTROLLER IrDA INTERUPT IDENTIFICATION REGISTER(IrDA_IIR) Register IrDA _IIR Address 0x41800010 R/W R Description IrDA Interrupt Identification Register Reset Value 0x00 IrDA _IIR Last byte to Rx FIFO Bit [7] Description Last byte write to RX FIFO interrupt pending. When the last payload byte of the frame is loaded into the RX FIFO, bit 7 is set to `1'. Bit 7 is set prior to bit 2. Bit 7 is cleared when it is read. Receiver line error Indication. Bit 6 is set to a `1' if one of three possible errors occurs in the RX process. With the corresponding interrupt enable bit active, one of PHY, CRC and Frame length errors let this bit go active. Bit 6 is cleared when the source of the error is cleared. Transmit under-run interrupt pending. When corresponding interrupt enable bit is active, bit 5 is set to `1' if an under-run occurs in TX FIFO. Bit 5 is cleared by serving the under-run. Detects last byte of a frame interrupt pending. If the corresponding interrupt enable bit is active, bit 4 is set to `1' when the demodulation block detects the last byte of a received frame and the CRC decoding is finished. Bit 4 is cleared when it is read. RX FIFO over-run interrupt. When corresponding interrupt enable bit is set, bit3 is active, bit 3 is set to `1' when an overrun occurs in the RX FIFO. Bit 3 is cleared by serving the over-run. RX FIFO last byte read interrupt. When corresponding interrupt enable bit is active, it is set to `1' when the CPU reads the last byte of a frame from the RX FIFO. It is cleared when it is read. TX FIFO below threshold interrupt pending. Bit 1 is set to `1' when the transmitter FIFO level is below its threshold level. RX FIFO over threshold interrupt pending. Bit 0 is set to `1' when the receiver FIFO level is equal to or above its threshold level. Initial State 0 Error indication [6] 0 Tx Underrun [5] 0 Last byte detect [4] 0 Rx overrun [3] 0 Last byte read from Rx FIFO [2] 0 Tx FIFO below threshold Rx FIFO over threshold [1] 0 [0] 0 12-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IRDA CONTROLLER S3C24A0 RISC MICROPROCESSOR IrDA LINE STATUS REGISTER(IrDA_LSR) Register Address IrDA _LSR 0x41800014 R/W R Description IrDA Line Status Register Reset Value 0x03 IrDA_LSR Tx empty Bit [7] Description Transmitter empty. This bit is set to `1' when TX FIFO is empty and the transmitter front-end is idle. Reserved Last byte received from RX FIFO. It is set to a `1' when the microcontroller reads the last byte of a frame from the RX FIFO and cleared when the MCU reads the IrDA_LSR register. Frame length error. It is set to `1' when a frame exceeding the maximum frame length predefined by IrDA_RXFLL and IrDA_RXFLH register is received. This bit is cleared when the microcontroller reads the IrDA_LSR register. When this error is detected, current frame reception is terminated. Data receiving is stopped until the next BOF is detected. Bit 4 is cleared to `0' when the IrDA_LSR register is read by the microcontroller. PHY error. In FIR mode, It is set to a `1' when an illegal 4PPM symbol is received. In IrDA_MIR mode, if an abort pattern(more than 7 consecutive `1's) is received during reception, this bit is set to `1'. It is cleared when microcontroller reads the LSR register. CRC error. Bit 2 is set to `1' when a bad IrDA_CRC is detected on data receive. It is cleared to `0' when microcontroller reads the LSR register. Reserved RX FIFO empty. It indicates that the RX FIFO is empty. When the state of RX FIFO turns into empty, it is set to `1'. When the RX FIFO is not empty, it is set to `0'. Initial State 1 Reserved Received last byte from Rx FIFO [6] [5] 0 0 Frame length error [4] 0 PHY error [3] 0 CRC error [2] 0 Reserved Rx FIFO empty [1] [0] 1 1 12-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IRDA CONTROLLER IrDA FIFO CONTROL REGISTER(IrDA_FCR) Register Address IrDA _FCR 0x41800018 R/W R/W Description IrDA FIFO Control Register Reset Value 0x00 IrDA _FCR Rx FIFO Trigger level select Bit [7:6] Description Receiver FIFO trigger level selection. Bit 7 0 0 1 1 Initial State 00 64-byte RX FIFO 01 16 32 56 Bit 6 0 1 0 1 16-byte RX FIFO 01 04 08 14 FIFO size select [5] When set to `1', 64 bytes TX and RX FIFO are selected. When set to `0', 16 bytes TX and RX FIFO are selected. 0 TX FIFO Clear Notification RX FIFO Clear Notification Tx FIFO reset [4] [3] [2] This bit will be activated when the FIFO clear is over. This bit is cleared by the CPU reads this register. This bit will be activated when the FIFO clear is over. This bit is cleared by the CPU reads this register. TX FIFO reset. When set to `1', bit 2 clears all bytes in the transmitter FIFO and reset its counter to `0'. A `1' written to bit 2 is self-clearing. RX FIFO reset. When set to `1', bit 1 clears all bytes in the receiver FIFO and reset its counter to `0'. A `1' written to bit 1 is self clearing. FIFO enable. When set to `1', bit 0 enables both the transmitter and receiver FIFOs. Bit 0 must be a `1' when setting other IrDA_FCR bits. Changing bit 0 clears the FIFO. 0 0 0 Rx FIFO reset [1] 0 FIFO enable [0] 0 12-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IRDA CONTROLLER S3C24A0 RISC MICROPROCESSOR IrDA PREAMBLE LENGTH REGISTER(IrDA_PLR) Register Address IrDA _PLR 0x4180001C R/W R/W Description IrDA Preamble Length Register Reset Value 0x12 REG_PLR Preamble length in FIR mode Bit [7:6] Description These two bits decide preamble length to be transmitted at the beginning of each frame in FIR mode. The default value of PLR[7:6] = `00' which is equal to 16 preambles. 00 : 16 01: 8 Bit 4 0 1 0 1 01 : 4 11: 32 Initial State 00 TX FIFO trigger level select [5:4] Transceiver FIFO trigger level selection. Bit 5 0 0 1 1 16-byte FIFO 64-byte FIFO Reserved 12 48 08 32 02 08 01 Note: Tx Trigger level value means how many data are empty. Number of start flags in MIR mode [3:0] Number of start flags in MIR mode. The number of start flags to be transmitted at the beginning of a frame is equal to the IrDA_PLR [3:0] value. The minimum value is 2. 0010 IrDA RECEIVER & TRANSMITTER BUFFER REGISTER(IrDA_RBR) Register IrDA_RBR Address 0x41800020 R/W R/W Description IrDA Receiver & Transmitter Buffer Register Reset Value 0x00 IrDA _RBR Rx/Tx data Bit [7:0] Description Received data (When read data) Data to transmit (When write data) Initial State 0x00 IrDA TOTAL NUMBER OF DATA BYTES REMAINED IN Tx FIFO(IrDA_TxNO) Register IrDA _TXNO Address 0x41800024 R/W R Description The total number of data bytes remained in Tx FIFO Reset Value 0x00 IrDA _TxNO Bit Description Initial State 12-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IRDA CONTROLLER Tx data total number [7:0] The total number of data bytes remained in Tx FIFO 0x00 IrDA TOTAL NUMBER OF DATA BYTES REMAINED IN Rx FIFO(IrDA_RxNO) Register Address R/W R Description The total number of data bytes remained in Rx FIFO Reset Value 0x00 IrDA _RxNO 0x41800028 IrDA _RxNO Rx data total number Bit [7:0] Description The total number of data bytes remained in Rx FIFO. Initial State 00 IrDA TRANSMIT FRAME-LENGTH REGISTER LOW(IrDA_TXFLL) Register Address IrDA _TXFLL 0x4180002C R/W R/W Description IrDA Transmit Frame-Length Register Low Reset Value 0x00 IrDA _TXFLL Tx frame length low Bit [7:0] Description TXFLL stores the lower 8 bits of the byte number of the frame to be transmitted. Initial State 00 IrDA TRANSMIT FRAME-LENGTH REGISTER HIGH(IrDA_TXFLH) Register Address IrDA _TXFLH 0x41800030 R/W R/W Description IrDA Transmit Frame-Length Register High Reset Value 0x00 IrDA _TXFLH Tx frame length high Bit [7:0] Description TXFLH stores the upper 8 bits of the byte number of the frame to be transmitted. Initial State 00 IrDA RECEIVER FRAME-LENGTH REGISTER LOW(IrDA_RXFLL) Register Address IrDA _RXFLL 0x41800034 R/W R/W Description IrDA Receive Frame-Length Register Low Reset Value 0x00 IrDA _RXFLL Rx frame length low Bit [7:0] Description RXFLL stores the lower 8 bits of the maximum byte number of the frame to be received. Initial State 00 12-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IRDA CONTROLLER S3C24A0 RISC MICROPROCESSOR IrDA RECEIVER FRAME-LENGTH REGISTER HIGH(IrDA_RXFLH) Register Address IrDA _RXFLH 0x41800038 R/W R/W Description IrDA Receive Frame-Length Register High Reset Value 0x00 IrDA _RXFLH Rx frame length high Bit [5:0] Description TXFLL stores the upper 6 bits of the maximum byte number of the frame to be received. Initial State 00 12-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE(Preliminary) OVERVIEW The S3C24A0 RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data line(SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus. The SDA and SCL lines are bi-directional. In multi-master IIC-bus mode, multiple S3C24A0 RISC microprocessors can receive or transmit serial data to or from slave devices. The master S3C24A0, which can initiate a data transfer over the IIC-bus, is responsible for terminating the transfer. Standard bus arbitration procedure is used in this IIC-bus in S3C24A0. To control multi-master IIC-bus operations, values must be written to the following registers: -- Multi-master IIC-bus control register, IICCON -- Multi-master IIC-bus control/status register, IICSTAT -- Multi-master IIC-bus Tx/Rx data shift register, IICDS -- Multi-master IIC-bus address register, IICADD -- Multi-master IIC-bus SDAOUT delay register, SDADLY When the IIC-bus is free, the SDA and SCL lines should be both at High level. A High-to-Low transition of SDA can initiate a Start condition. A Low-to-High transition of SDA can initiate a Stop condition while SCL remains steady at High Level. The Start and Stop conditions can always be generated by the master devices. A 7-bit address value in the first data byte, which is put onto the bus after the Start condition has been initiated, can determine the slave device which the bus master device has selected. The 8th bit determines the direction of the transfer (read or write). Every data byte put onto the SDA line should total eight bits. The number of bytes which can be sent or received during the bus transfer operation is unlimited. Data is always sent from most-significant bit (MSB) first, and every byte should be immediately followed by an acknowledge (ACK) bit. 13-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIC-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR Address Register Comparator IIC-Bus Control Logic SCL PCLK IICCON IICSTAT 4-bit Prescaler Shift Register SDA Shift Register (IICDS) Data Bus Figure 13-1. IIC-Bus Block Diagram 13-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIC-BUS INTERFACE THE IIC-BUS INTERFACE The S3C24A0 IIC-bus interface has four operation modes: -- Master transmitter mode -- Master receive mode -- Slave transmitter mode -- Slave receive mode Functional relationships among these operating modes are described below. START AND STOP CONDITIONS When the IIC-bus interface is inactive, it is usually in slave mode. In other words, the interface should be in slave mode before detecting a Start condition on the SDA line.(A Start condition can be initiated with a High-to-Low transition of the SDA line while the clock signal of SCL is High) When the interface state is changed to the master mode, a data transfer on the SDA line can be initiated and SCL signal generated. A Start condition can transfer a one-byte serial data over the SDA line, and a stop condition can terminate the data transfer. A stop condition is a Low-to-High transition of the SDA line while SCL is High. Start and Stop conditions are always generated by the master. The IIC-bus is busy when a Start condition is generated. A few clocks after a Stop condition, the IIC-bus will be free, again. When a master initiates a Start condition, it should send a slave address to notify the slave device. The one byte of address field consist of a 7-bit address and a 1-bit transfer direction indicator (that is, write or read). If bit 8 is 0, it indicates a write operation(transmit operation); if bit 8 is 1, it indicates a request for data read(receive operation). The master will finish the transfer operation by transmitting a Stop condition. If the master wants to continue the data transmission to the bus, it should generate another Start condition as well as a slave address. In this way, the read-write operation can be performed in various formats. SDA SDA SCL SCL Start Condition Stop Condition Figure 13-2. Start and Stop Condition 13-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIC-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The number of bytes which can be transmitted per transfer is unlimited. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in master mode. Each byte should be followed by an acknowledgement (ACK) bit. The MSB bit of the serial data and addresses are always sent first. Write Mode Format with 7-bit Addresses S Slave Address 7bits R/W A "0" (Write) DATA(1Byte) AP Data Transferred (Data + Acknowledge) Write Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "0" (Write) Slave Address 2nd Byte A DATA AP Data Transferred (Data + Acknowledge) Read Mode Format with 7-bit Addresses S Slave Address 7 bits R/W A "1" (Read) DATA AP Data Transferred (Data + Acknowledge) Read Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "1" (Read) Slave Address 2nd Byte A rS Slave Address 1st 7 Bits R/W A "1" (Read) DATA AP Data Transferred (Data + Acknowledge) NOTES: 1. S: Start, rS: Repeat Start, P: Stop, A: Acknowledge 2. : From Master to Slave, : from Slave to Master Figure 13-3. IIC-Bus Interface Data Format 13-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIC-BUS INTERFACE SDA MSB Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver SCL S 1 2 7 8 9 ACK 1 2 9 Byte Complete, Interrupt within Receiver Clock Line Held Low While Interrupts are Serviced Figure 13-4. Data Transfer on the IIC-Bus ACK SIGNAL TRANSMISSION To finish a one-byte transfer operation completely, the receiver should send an ACK bit to the transmitter. The ACK pulse should occur at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master should generate the clock pulse required to transmit the ACK bit. The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received. The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA is Low during the High period of the ninth SCL pulse. The ACK bit transmit function can be enabled or disabled by software (IICSTAT). However, the ACK pulse on the ninth clock of SCL is required to complete a one-byte data transfer operation. Clock to Output Data Output by Transmitter Data Output by Receiver SCL from Master S Start Condition 1 2 7 8 9 Clock Pulse for Acknowledgment Figure 13-5. Acknowledge on the IIC-Bus 13-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIC-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR READ-WRITE OPERATION In the transmitter mode, after the data is transferred, the IIC-bus interface will wait until IICDS(IIC-bus Data Shift Register) is written by a new data. Until the new data is written, the SCL line will be held low. After the new data is written to IICDS register, the SCL line will be released. The S3C24A0 should hold the interrupt to identify the completion of current data transfer. After the CPU receives the interrupt request, it should write a new data into IICDS, again. In the receive mode, after a data is received, the IIC-bus interface will wait until IICDS register is read. Until the new data is read out, the SCL line will be held low. After the new data is read out from IICDS register, the SCL line will be released. The S3C24A0 should hold the interrupt to identify the completion of the new data reception. After the CPU receives the interrupt request, it should read the data from IICDS. BUS ARBITRATION PROCEDURES Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master with a SDA High level detects another master with a SDA active Low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. The arbitration procedure will be extended until the SDA line turns High. However when the masters simultaneously lower the SDA line, each master should evaluate whether or not the mastership is allocated to itself. For the purpose of evaluation, each master should detect the address bits. While each master generates the slaver address, it should also detect the address bit on the SDA line because the lowering of SDA line is stronger than maintaining High on the line. For example, one master generates a Low as first address bit, while the other master is maintaining High. In this case, both masters will detect Low on the bus because Low is stronger than High even if first master is trying to maintain High on the line. When this happens, Low(as the first bit of address) -generating master will get the mastership and High(as the first bit of address) generating master should withdraw the mastership. If both masters generate Low as the first bit of address, there should be an arbitration for second address bit, again. This arbitration will continue to the end of last address bit. ABORT CONDITIONS If a slave receiver can not acknowledge the confirmation of the slave address, it should hold the level of the SDA line High. In this case, the master should generate a Stop condition and to abort the transfer. If a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by canceling the generation of an ACK after the last data byte received from the slave. The slave transmitter should then release the SDA to allow a master to generate a Stop condition. CONFIGURING THE IIC-BUS To control the frequency of the serial clock (SCL), the 4-bit prescaler value can be programmed in the IICCON register. The IIC-bus interface address is stored in the IIC-bus address register, IICADD. (By default, the IIC-bus interface address is an unknown value.) 13-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIC-BUS INTERFACE FLOWCHARTS OF THE OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1) Write own slave address on IICADD register if needed. 2) Set IICCON Register. a) Enable interrupt b) Define SCL period 3) Set IICSTAT to enable Serial Output START Master Tx mode has been configured. Write slave address to IICDS Write 0xF0(M/T Start) to IICSTAT The data of the IICDS is transmitted ACK period and then interrupt is pending Y Stop? N Write new data transmitted to IICDS Clear pending bit to resume The data of the IICDS is shifted to SDA Write 0xD0(M/T Stop) to IICSTAT Clear pending bit Wait until the stop condition takes effect. END Figure 13-6 Operations for Master / Transmitter Mode 13-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIC-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR START Master Rx mode has been configured. Write slave address to IICDS Write 0xB0(M/R Start) to IICSTAT The data of the IICDS(slave address) is transmitted ACK period and then interrupt is pending Y Stop? N Read a new data from IICDS Clear pending bit to resume Write 0x90(M/R Stop) to IICSTAT Clear pending bit SDA is shifted to IICDS Wait until the stop condition takes effect. END Figure 13-7 Operations for Master / Receiver Mode 13-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIC-BUS INTERFACE START Slave Tx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS(the received slave address) N Matched? Y The IIC address match interrupt is generated Write data to IICDS Clear pending bit to resume. Y Stop? N The data of the IICDS is shifted to SDA END Interrupt is pending Figure 13-8 Operations for Slave / Transmitter Mode 13-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIC-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR START Slave Rx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS(the received slave address) N Matched? Y The IIC address match interrupt is generated Read data from IICDS Clear pending bit to resume. Y Stop? N SDA is shifted to IICDS END Interrupt is pending Figure 13-9 Operations for Slave / Receiver Mode 13-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE SPECIAL REGISTERS MULTI-MASTER IIC-BUS CONTROL REGISTER (IICCON) Register IICCON Address 0x44600000 R/W R/W Description IIC-Bus control register Reset Value 0x0X IICCON Acknowledge generation (1) Bit [7] Description IIC-bus acknowledge enable bit 0 = Disable 1 = Enable In Tx mode, the IICSDA is free in the ack time. In Rx mode, the IICSDA is L in the ack time. Initial State 0 Tx clock source selection [6] Source clock of IIC-bus transmit clock prescaler selection bit 0 = IICCLK = fPCLK /16 1 = IICCLK = fPCLK /512 IIC-Bus Tx/Rx interrupt enable/disable bit 0 = Disable, 1 = Enable IIC-bus Tx/Rx interrupt pending flag. Writing 1 is impossible. When this bit is read as 1, the IICSCL is tied to L and the IIC is stopped. To resume the operation, clear this bit as 0. 0 = 1) No interrupt pending(when read), 2) Clear pending condition & Resume the operation (when write). 1 = 1) Interrupt is pending (when read) 2) N/A (when write) 0 Tx/Rx Interrupt (5) [5] [4] 0 0 Interrupt pending flag (2) (3) Transmit clock value (4) [3:0] IIC-Bus transmit clock prescaler IIC-Bus transmit clock frequency is determined by this 4-bit prescaler value, according to the following formula: Tx clock = IICCLK/(IICCON[3:0]+1) Undefined NOTES: 1. Interfacing with EEPROM, the ack generation may be disabled before reading the last data in order to generate the STOP condition in Rx mode. 2. A IIC-bus interrupt occurs 1)when a 1-byte transmit or receive operation is completed, 2)when a general call or a slave address match occurs, or 3) if bus arbitration fails. 3. To time the setup time of IICSDA before IISSCL rising edge, IICDS has to be written before clearing the IIC interrupt pending bit. 4. IICCLK is determined by IICCON[6]. Tx clock can vary by SCL transition time. When IICCON[6]=0, IICCON[3:0]=0x0 or 0x1 is not available. 5. If the IICON[5]=0, IICON[4] does not operate correctly. So, It is recommended to set IICCON[4]=1, although you does not use the IIC interrupt. 13-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIC-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR MULTI-MASTER IIC-BUS CONTROL/STATUS REGISTER (IICSTAT) Register IICSTAT Address 0x44600004 R/W R/W Description IIC-Bus control/status register Reset Value 0x0 IICSTAT Mode selection Bit [7:6] Description IIC-bus master/slave Tx/Rx mode select bits: 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode IIC-Bus busy signal status bit: 0 = read) Not busy write) STOP signal generate(only for master) 1 = read) Busy write) START signal generate(only for master) The data in IICDS will be transferred automatically just after the start signal. IIC-bus data output enable/disable bit: 0 = Disable Rx/Tx 1 = Enable Rx/Tx IIC-bus arbitration procedure status flag bit: 0 = Bus arbitration successful 1 = Bus arbitration failed during serial I/O IIC-bus address-as-slave status flag bit: 0 = Cleared when START/STOP condition was detected 1 = Received slave address matches the address value in the IICADD. IIC-bus address zero status flag bit: 0 = Cleared when START/STOP condition was detected. 1 = Received slave address is 00000000b IIC-bus last-received bit status flag bit 0 = Last-received bit is 0 (ACK was received) 1 = Last-received bit is 1 (ACK was not received) Initial State 00 Busy signal status / START STOP condition [5] 0 Serial output Arbitration status flag [4] [3] 0 0 Address-as-slave status flag [2] 0 Address zero status flag [1] 0 Last-received bit status flag [0] 0 13-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIC-BUS INTERFACE MULTI-MASTER IIC-BUS ADDRESS REGISTER (IICADD) Register IICADD Address 0x44600008 R/W R/W Description IIC-Bus address register Reset Value 0xXX IICADD Slave address Bit [7:0] Description 7-bit slave address, latched from the IIC-bus : When serial output enable = 0 in the IICSTAT, IICADD is write-enabled. The IICADD value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting. Slave address = [7:1] Not mapped = [0] Initial State XXXXXXXX MULTI-MASTER IIC-BUS TRANSMIT/RECEIVE DATA SHIFT REGISTER (IICDS) Register IICDS Address 0x4460000C R/W R/W Description IIC-Bus transmit/receive data shift register Reset Value 0xXX IICDS Data shift Bit [7:0] Description 8-bit data shift register for IIC-bus Tx/Rx operation : When serial output enable = 1 in the IICSTAT, IICDS is write-enabled. The IICDS value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting Initial State XXXXXXXX MULTI-MASTER IIC-BUS SDAOUT DELAY REGISTER (SDADLY) Register SDADLY Address 0x44600010 R/W R/W Description IIC-Bus SDAOUT delay register Reset Value 0x0 SDADLY FLTEN SDADLY Bit [2] [1:0] 0= Disable 00= 0-cycle 10= 10-cycle Description SCL & SDA line input filter enable 1= Enable Delay setting for IIC-bus SDA output operation: 01= 5-cycle 11= 15-cycle Initial State 0 0 13-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIC-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR NOTES 13-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIS-BUS INTERFACE IIS-BUS INTERFACE(PRELIMINARY) OVERVIEW Many digital audio systems are introduced into the consumer audio market, including compact disc, digital audio tapes, digital sound processors, and digital TV sound. The S3C24A0 IIS(Inter-IC Sound) bus interface can be used to implement a CODEC interface to an external 8/16-bit stereo audio CODEC IC for mini-disc and portable applications. It supports the IIS bus data format and MSB-justified data format. IIS bus interface provides DMA transfer mode for FIFO access instead of an interrupt. It can transmit or receive data simultaneously as well as transmit or receive data only. FEATURES -- IIS, MSB-justified format compatible -- 8/16-bit data per channel -- 16, 32, 48fs(sampling frequency) serial bit clock per channel -- 256, 384fs master clock -- Programmable frequency divider for master clock and CODEC clock -- 128 bytes(2 X 64) FIFO for transmit and receive -- Normal and DMA transfer mode 14-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIS-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR BLOCK DIAGRAM ADDR DATA CNTL BRFC TxFIFO SFTR RxFIFO CHNC SD IPSR_A PCLK IPSR_B SCLK SCLKG LRCK CDCLK Figure 14-1. IIS-Bus Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface, register bank, and state machine(BRFC) - Bus interface logic and FIFO access are controlled by the state machine. 5-bit dual prescaler(IPSR) - One prescaler is used as the master clock generator of the IIS bus interface and the other is used as the external CODEC clock generator. 64-byte FIFOs(TxFIFO, RxFIFO) - In transmit data transfer, data are written to TxFIFO, and, in the receive data transfer, data are read from RxFIFO. Master IISCLK generator(SCLKG) - In master mode, serial bit clock is generated from the master clock. Channel generator and state machine(CHNC) - IISCLK and IISLRCK are generated and controlled by the channel state machine. 16-bit shift register(SFTR) - Parallel data is shifted to serial data output in the transmit mode, and serial data input is shifted to parallel data in the receive mode. TRANSMIT OR RECEIVE ONLY MODE Normal transfer IIS control register has FIFO ready flag bits for transmit and receive FIFO. When FIFO is ready to transmit data, the FIFO ready flag is set to '1' if transmit FIFO is not empty. If transmit FIFO is empty, FIFO ready flag is set to '0'. When receive FIFO is not full, the FIFO ready flag for receive FIFO is set to '1' ; it indicates that FIFO is ready to receive data. If receive FIFO is full, FIFO ready flag is set to '0'. These flags can determine the time that CPU is to write or read FIFOs. Serial data can be transmitted or received while CPU is accessing transmit and receive FIFOs in this way. 14-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIS-BUS INTERFACE DMA TRANSFER In this mode, transmit or receive FIFO access is made by the DMA controller. DMA service request in transmit or receive mode is made by the FIFO ready flag automatically. TRANSMIT AND RECEIVE MODE In this mode, IIS bus interface can transmit and receive data simultaneously. AUDIO SERIAL INTERFACE FORMAT IIS-BUS FORMAT The IIS bus has four lines, serial data input(IISDI), serial data output(IISDO), left/right channel select(IISLRCK), and serial bit clock(IISCLK); the device generating IISLRCK and IISCLK is the master. Serial data is transmitted in 2's complement with the MSB first. The MSB is transmitted first because the transmitter and receiver may have different word lengths. It is not necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. When the system word length is greater than the transmitter word length, the word is truncated(least significant data bits are set to '0') for data transmission. If the receiver is sent more bits than its word length, the bits after the LSB are ignored. On the other hand, if the receiver is sent fewer bits than its word length, the missing bits are set to zero internally. And so, the MSB has a fixed position, whereas the position of the LSB depends on the word length. The transmitter always sends the MSB of the next word at one clock period after the IISLRCK change. Serial data sent by the transmitter may be synchronized with either the trailing (HIGH to LOW) or the leading (LOW to HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge. The LR channel select line indicates the channel being transmitted. IISLRCK may change either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The IISLRCK line changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear the input for the next word. MSB(LEFT) JUSTIFIED MSB / left justified bus has the same lines as the IIS format. It is only different with the IIS bus that transmitter always sends the MSB of the next word when the IISLRCK change. 14-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIS-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR LRCK LEFT RIGHT LEFT SCLK MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) SD IIS-BUS FORMAT (N=8 or 16) LRCK LEFT RIGHT SCLK MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) SD MSB-JUSTIFIED FORMAT (N=8 or 16) Figure 14-2. IIS-Bus and MSB(Left)-justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency(PCLK) can be selected by sampling frequency as shown in Table 21-1. Because PCLK is made by IIS prescaler, the prescaler value and PCLK type(256 or 384fs) should be determined properly. Serial bit clock frequency type(16/32/48fs) can be selected by the serial bit per channel and PCLK as shown in Table 21-2. Table 14-1 CODEC clock (IISCDCLK = 256 or 384fs) IISLRCK (fs) IISCDCLK (MHz) 8.000 KHz 256fs 2.0480 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 11.025 KHz 16.000 KHz 22.050 KHz 32.000 KHz 44.100 KHz 48.000 KHz 64.000 KHz 88.200 KHz 96.000 KHz Table 14-2 Usable serial bit clock frequency (IISCLK = 16 or 32 or 48fs) Serial bit per channel Serial clock frequency (IISCLK) @IISCDCLK = 256fs @IISCDCLK = 384fs 16fs, 32fs 16fs, 32fs, 48fs 32fs 32fs, 48fs 8-bit 16-bit 14-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIS-BUS INTERFACE IIS-BUS INTERFACE SPECIAL REGISTERS IIS CONTROL REGISTER (IISCON) Register IISCON 0x44700000 Address R/W R/W Description IIS control register Reset Value 0x100 IISCON Left/Right channel index (Read only) Transmit FIFO ready flag (Read only) Receive FIFO ready flag (Read only) Transmit DMA service request Receive DMA service request Transmit channel idle command Bit [8] [7] [6] [5] [4] [3] 0 = Left 1 = Right 0 = Empty 1 = Not empty 0 = Full 1 = Not full 0 = Disable 1 = Enable 0 = Disable 1 = Enable Description Initial State 1 0 0 0 0 0 In Idle state the IISLRCK is inactive(Pause Tx) 0 = Not idle 1 = Idle In Idle state the IISLRCK is inactive(Pause Rx) 0 = Not idle 1 = Idle 0 = Disable 1 = Enable 0 = Disable (stop) 1 = Enable (start) Receive channel idle command [2] 0 IIS prescaler IIS interface [1] [0] 0 0 14-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIS-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR IIS MODE REGISTER (IISMOD) Register IISMOD Address 0x44700004 R/W R/W Description IIS mode register Reset Value 0x0 IISMOD Master/slave mode select Transmit/receive mode select Active level of left/right channel Serial interface format Serial data bit per channel Master clock frequency select Serial bit clock frequency select Bit [8] [7:6] [5] [4] [3] [2] [1:0] Description 0 = Master mode (IISLRCK and IISCLK are output mode) 1 = Slave mode (IISLRCK and IISCLK are input mode) 00 = No transfer 10 = Transmit mode 01 = Receive mode 11 = Transmit and receive mode Initial State 0 00 0 0 0 0 00 0 = Low for left channel (High for right channel) 1 = High for left channel (Low for right channel) 0 = IIS compatible format 1 = MSB(Left)-justified format 0 = 8-bit 1 = 16-bit 0 = 256fs 1 = 384fs (fs : sampling frequency) 00 = 16fs 10 = 48fs 01 = 32fs 11 = N/A 14-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR IIS-BUS INTERFACE IIS PRESCALER REGISTER (IISPSR) Register IISPSR 0x44700008 Address R/W R/W Description IIS prescaler register Reset Value 0x0 IISPSR Prescaler control A Bit [9:5] Data value : 0 ~ 31 Description NOTE : Prescaler A makes the master clock that is used the internal block and division factor is N+1. Initial State 00000 Prescaler control B [4:0] Data value : 0 ~ 31 NOTE : Prescaler B makes the master clock that is used the external block and division factor is N+1. 00000 IIS FIFO CONTROL REGISTER (IISFCON) Register IISFCON Address 0x4470000C R/W R/W Description IIS FIFO interface register Reset Value 0x0 IISFCON Transmit FIFO access mode select Receive FIFO access mode select Transmit FIFO Receive FIFO Transmit FIFO data count (Read only) Receive FIFO data count (Read only) Bit [15] [14] [13] [12] [11:6] [5:0] 0 = Normal 1 = DMA 0 = Normal 1 = DMA 0 = Disable 0 = Disable Description Initial State 0 0 1 = Enable 1 = Enable 0 0 000000 000000 Data count value = 0 ~ 32 Data count value = 0 ~ 32 IIS FIFO REGISTER (IISFIFO) IIS bus interface contains two 64-byte FIFO for the transmit and receive mode. Each FIFO has 16-width and 32depth form, which allows the FIFO to handles data by halfword unit regardless of valid data size. Transmit and receive FIFO access is performed through FIFO entry; the address of FENTRY is 0x44700010 Register IISFIFO Address 0x44700010 R/W R/W Description IIS FIFO register Reset Value 0x0 IISFIFO FENTRY Bit [15:0] Description Transmit/Receive data for IIS Initial State 0x0 14-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 IIS-BUS INTERFACE S3C24A0 RISC MICROPROCESSOR 14-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SPI INTERFACE SPI INTERFACE (PRELIMINARY) OVERVIEW The S3C24A0 Serial Peripheral Interface(SPI) can interface the serial data transfer. There are two SPI in S3C24A0 and each SPI has two 8bit shift register for transmission and receiving, respectively. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially) 8bit serial data at a frequency determined by its corresponding control register settings. If you want only to transmit, you may treat the received data as dummy. Otherwise, if you want only to receive, you should transmit dummy '1' data. There are 4 I/O pin signals associated with SPI transfers: the SCK, the MISO data line, the MOSI data line, and the active low /SS pin(input). FEATURES -- SPI Protocol(ver 2.11) compatible -- 8-bit Shift Register for transmit -- 8-bit Shift Register for receive -- 8-bit Prescaler logic -- Polling, Interrupt, and DMA transfer mode 15-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SPI INTERFACE S3C24A0 RISC MICROPROCESSOR BLOCK DIAGRAM 8 Data Bus 8 LSB MSB SPIMISO 0 Slave Master Master Slave Clock MISO Tx 8bit Shift Reg 0 MSB LSB Rx 8bit Shift Reg 0 Pin Control Logic 0 SPIMOSI 0 MOSI PCLK 8bit Prescaler 0 SPI Clock (Master) CPOL CPHA CLOCK Logic 0 SPICLK 0 SCK Slave Master Prescaler Register 0 Status Register 0 DCOL REDY MULF nSS 0 Slave /SS INT 0 / INT 1 REQ0 / REQ1 ACK0 / ACK1 MSTR APB I/F 0 (INT DMA 0) 8 LSB MSB SPIMISO 1 Slave Master Master Slave Clock MISO Tx 8bit Shift Reg 1 8 Rx 8bit Shift Reg 1 Pin Control Logic 1 MSB LSB SPIMOSI 1 MOSI PCLK 8bit Prescaler 1 SPI Clock (Master) CPOL CPHA CLOCK Logic 1 SPICLK 1 SCK Slave Master Prescaler Register 1 Status Register 1 DCOL MULF REDY nSS 1 Slave /SS INT 0 / INT 1 REQ0 / REQ1 ACK0 / ACK1 MSTR APB I/F 1 (INT DMA 1) Figure 15-1. SPI Block Diagram 15-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SPI INTERFACE SPI OPERATION Using the SPI interface, 8-bit data can be sending and receiving data simultaneously with an external device. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. When SPI is the master, transmission frequency can be controlled by setting the appropriate bit to SPPREn register. You can modify its frequency to adjust the baud rate data register value. When SPI is a slave, other master supplies the clock. When a programmer writes byte data to SPTDATn register, SPI transmit and receive operation will start simultaneously. In some cases, nSS should be activated before writing byte data to SPTDATn. Programming Procedure When a byte data is written into the SPTDATn register, SPI starts to transmit if ENSCK and MSTR of SPCONn register are set. There is a typical programming procedure to operate an SPI card. To program the SPI modules, follow these basic steps : 1. Set Baud Rate Prescaler Register(SPPREn) 2. Set SPCONn to configure properly the SPI module 3. Write data 0xFF to SPTDATn 10 times in order to initialize MMC or SD card 4. Set a GPIO pin, which acts as nSS, to low to activate the MMC or SD card. 5. Tx data Check the status of Transfer Ready flag (REDY=1), and then write data to SPTDATn. 6. Rx data(1) : SPCONn's TAGD bit disable = normal mode write 0xFF to SPTDATn, then confirm REDY to set, and then read data from Read Buffer 7. Rx data(2) : SPCONn's TAGD bit enable = Tx Auto Garbage Data mode confirm REDY to set, and then read data from Read Buffer(then automatically start to transfer) 8. Set a GPIO pin, which acts as nSS, to high, to deactivate MMC or SD card. 15-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SPI INTERFACE S3C24A0 RISC MICROPROCESSOR SPI Transfer Format S3C24A0 supports 4 different format to transfer the data. Four waveforms are shown for SPICLK. CPOL = 0, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB MSB* 1 2 3 4 5 6 7 8 * MSB of character just received CPOL = 0, CPHA = 1 (Format B) Cycle SPICLK MOSI MISO *LSB MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB* 1 2 3 4 5 6 7 8 * LSB of previously transmitted character CPOL = 1, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB MSB* 1 2 3 4 5 6 7 8 * MSB of character just received CPOL = 1, CPHA = 1 (Format B) Cycle SPICLK MOSI MISO MSB *LSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB 1 2 3 4 5 6 7 8 * LSB of previously transmitted character Figure 15-2. SPI Transfer Format 15-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SPI INTERFACE Steps for Transmit by DMA 1. The SPI is configured as DMA mode. 2. DMA is configured properly. 3. The SPI requests DMA service. 4. DMA transmits 1byte data to the SPI. 5. The SPI transmits the data to card. 6. Go to step 3 until DMA count is 0. 7. The SPI is configured as interrupt or polling mode with SMOD bits. Steps for Receive by DMA 1. The SPI is configured as DMA start with SMOD bits and setting TAGD bit. 2. DMA is configured properly. 3. The SPI receives 1byte data from card. 4. The SPI requests DMA service. 5. DMA receives the data from the SPI. 6. Write data 0xFF automatically to SPTDATn. 7. Go to step 4 until DMA count is 0. 8. The SPI is configured as polling mode with SMOD bits and clearing TAGD bit. 9. If SPSTAn's REDY flag is set, then read the last byte data. NOTE: Total received data = DMA TC values + The last data in polling mode(step 9). First DMA received data is dummy, so user can neglect that. 15-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SPI INTERFACE S3C24A0 RISC MICROPROCESSOR SPI SPECIAL REGISTERS SPI CONTROL REGISTER Register SPCON0 SPCON1 Address 0x44500000 0x44500020 Bit [6:5] R/W R/W R/W Description SPI Channel 0 Control Register SPI Channel 1 Control Register Reset Value 0x00 0x00 Initial State 00 SPCONn SPI Mode Select (SMOD) SCK Enable (ENSCK) Master/Slave Select(MSTR) [4] [3] Clock Polarity Select(CPOL) Clock Phase Select(CPHA) Tx Auto Garbage Data mode enable (TAGD) [2] [1] [0] Description Determines how and by what SPTDAT is read/written 00 = polling mode, 01 = interrupt mode 10 = DMA mode, 11 = reserved Determines what you want SCK enable or not(only master) 0 = disable, 1 = enable Determines what mode you want master or slave 0 = slave, 1 = master NOTE: In slave mode, there should be set up time for master to initiate Tx / Rx. Determines an active high or active low clock. 0 = active high, 1 = active low This bit selects one of two fundamentally different transfer formats. 0 = format A, 1 = format B This bit decides whether the receiving data only needs or not. 0 = normal mode, 1 = Tx auto garbage data mode NOTE: In normal mode, you only want to receive data, you should transmit dummy 0xFF data. 0 0 0 0 0 15-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SPI INTERFACE SPI STATUS REGISTER Register SPSTA0 SPSTA1 Address 0x44500004 0x44500024 Bit [7:3] [2] R/W R R Description SPI Channel 0 Status Register SPI Channel 1 Status Register Description This flag is set if the SPTDATn is written or the SPRDATn is read while a transfer is in progress and cleared by reading the SPSTAn. 0 = not detect, 1 = collision error detect This flag is set if the nSS signal goes to active low while the SPI is configured as a master, and SPPINn's ENMUL bit is multi master errors detect mode. MULF is cleared by reading SPSTAn. 0 = not detect, 1 = multi master error detect This bit indicates that SPTDATn or SPRDATn is ready to transmit or receive. This flag is automatically cleared by writing data to SPTDATn. 0 = not ready, 1 = data Tx/Rx ready Reset Value 0x01 0x01 Initial State 0 SPSTAn Reserved Data Collision Error Flag(DCOL) Multi Master Error Flag (MULF) [1] 0 Transfer Ready Flag (REDY) [0] 1 15-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SPI INTERFACE S3C24A0 RISC MICROPROCESSOR SPI PIN CONTROL REGISTER When the SPI system is enabled, the direction of pins is controlled by MSTR bit of SPCONn register except nSS pin. The direction of nSS pin is input always. When the SPI is a master, nSS pin is used to check multi-master error, provided the SPPIN's ENMUL bit is active, and another GPIO should be used to select a slave. If the SPI is configured as a slave, nSS pin is used to select SPI as a slave by one master. Register SPPIN0 SPPIN1 SPPINn Reserved Multi Master error detect Enable (ENMUL) Reserved Master Out Keep(KEEP) Address 0x44500008 0x44500028 Bit [7:3] [2] R/W R/W R/W Description SPI Channel 0 Pin Control Register SPI Channel 1 Pin Control Register Description The /SS pin is used as an input to detect multi master error when the SPI system is a master. 0 = disable(general purpose), 1 = multi master error detect enable This bit should be `1'. Determines MOSI drive or release when 1byte transmit finish(only master) 0 = release, 1 = drive the previous level Reset Value 0x02 0x02 Initial State 0 [1] [0] 1 0 The SPIMISO(MISO) and SPIMOSI(MOSI) data pins are used for transmitting and receiving serial data. When the SPI is configured as a master, SPIMISO(MISO) is the master data input line, SPIMOSI(MOSI) is the master data output line, and SPICLK(SCK) is the clock output line. When as a slave, these pins reverse roles. In a multiplemaster system, all SPICLK(SCK) pins are tied together, all SPIMOSI(MOSI) pins are tied together, and all SPIMISO(MISO) pins are tied together. Only an SPI master can experience a multi master error, caused when a second SPI device becomes a master and selects this device as if it were a slave. When this type error is detected, the following actions are taken immediately. But you must previously set SPPINn's ENMUL bit if you want to detect this error. 1. The SPCONn's MSTR bit is forced to 0 to operate slave mode. 2. The SPSTAn's MULF flag is set, and an SPI interrupt is generated. 15-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SPI INTERFACE SPI Baud Rate Prescaler Register Register SPPRE0 SPPRE1 Address 0x4450000C 0x4450002C Bit [7:0] R/W R/W R/W Description SPI Cannel 0 Baud Rate Prescaler Register SPI Cannel 1 Baud Rate Prescaler Register Reset Value 0x00 0x00 Initial State 0x00 Description Determines SPI clock rate as above equation. Baud rate = PCLK / 2 / (Prescaler value + 1) NOTE: Baud rate should be less than 25MHz. SPPREn Prescaler Value SPI Tx Data Register Register SPTDAT0 SPTDAT1 Address 0x44500010 0x44500030 Bit [7:0] R/W R/W R/W Description SPI Channel 0 Tx Data Register SPI Channel 1 Tx Data Register Reset Value 0x00 0x00 Initial State 0x00 SPTDATn Tx Data Register Description This field contains the data to be transmitted over the SPI channel SPI Rx Data Register Register SPRDAT0 SPRDAT1 Address 0x44500014 0x44500034 Bit [7:0] R/W R R Description SPI Channel 0 Rx Data Register SPI Channel 1 Rx Data Register Reset Value 0x00 0x00 Initial State 0x00 SPRDATn Rx Data Register Description This field contains the data to be received over the SPI channel 15-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SPI INTERFACE S3C24A0 RISC MICROPROCESSOR NOTES 15-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR AC97 CONTROLLER AC97 CONTROLLER OVERVIEW The AC97 Controller Unit of S3C24A0 supports the AC97 revision 2.0 features. AC97 Controller communicates with AC97 Codec using audio controller link (AC-link). Controller sends the stereo PCM data to Codec. The external digital-to-analog converter (DAC) in the Codec then converts the audio sample to an analog audio waveform. Also, Controller receives the stereo PCM data and the mono MIC data from Codec then store in memories. This chapter describes the programming model for the AC97 Controller Unit. The information in this chapter requires an understanding of the AC97 revision 2.0 specification. FEATURE _ _ _ _ _ _ Independent channels for stereo PCM In, stereo PCM Out, mono MIC In. 32bit (16-bit x 2), 16 entries for stereo PCM In, stereo PCM Out and 16bit, 16 entries for MIC In. All of the channels support only 16-bit sample lengths. Variable sampling rate AC97 Codec interface (48KHz and below) DMA-based operation and interrupt based operation. Only primary Codec support. 16-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 AC97 CONTROLLER S3C24A0 RISC MICROPROCESSOR AC97 CONTROLLER OPERATION BLOCK DIAGRAM Figure 16-1 shows the functional block diagram of S3C24A0 AC97 Controller. The AC97 signals form the AC-link, which is a point-to-point synchronous serial interconnection that supports full-duplex data transfers. All digital audio streams and command/status information are communicated over the AC-link. SFR FSM & Control APB APB I/F DMA Engine PCM in FIFO PCM out FIFO AC-link I/F AC-link Interrupt Control MIC in FIFO Figure 16-1 AC97 Block Diagram 16-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR AC97 CONTROLLER INTERNAL DATA PATH Figure 16-2 shows the internal data path of S3C24A0 AC97 Controller. It has stereo Pulse Code Modulated (PCM) In, Stereo PCM Out and mono MIC-in buffers, which consist of 16-bit, 16 entries buffer. Also it has 20-bit I/O shift register via AC-link. Command Addr Register Command Data Register PWDATA PCM Out Buffer (Regfile 16 bit x 2 x 16 Entry) PCM In Buffer (Regfile 16 bit x 2 x 16 Entry) Mic In Buffer (RegFile 16 bit x16 Entry) Output Shift Register (20 bit) Input Shift Register (20 bit) SDATA_OUT SDATA_IN PRDATA Response Data Register Figure 16-2. Internal Data Path 16-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 AC97 CONTROLLER S3C24A0 RISC MICROPROCESSOR OPERATION FLOW CHART System reset or Cold reset Set GPIO and Release INTMSK/SUBINTMSK bits Enable Codec Ready interrupt No No Time out condition ? Codec Ready interrupt ? Yes Controller off Disable Codec Ready interrupt DMA operation or PIO (Interrupt or Polling) operation Figure 16-3. AC97 Operation Flow Chart 16-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR AC97 CONTROLLER AC-LINK DIGITAL INTERFACE PROTOCOL Each AC97 Codec incorporates a five-pin digital serial interface that links it to the S3C24A0 AC97 Controller. AClink is a full-duplex, fixed-clock, PCM digital stream. It employs a time division multiplexed (TDM) scheme to handle control register accesses and multiple input and output audio streams. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams. Each stream has 20-bit sample resolution and requires a DAC and an analog-to-digital converter (ADC) with a minimum 16-bit resolution. Slot # (256-bit) SYNC SDATA_OUT SDATA_IN 0 1 2 3 4 5 6 7 8 9 10 11 12 TAG 16-bit TAG CMD ADDR 20-bit CMD DATA 20-bit PCM PCM L FRONT R FRONT 20-bit PCM LEFT 20-bit PCM RIGHT RSRVD RSRVD 20-bit RSRVD 20-bit PCM MIC RSRVD 20-bit RSRVD RSRVD 20-bit RSRVD RSRVD 20-bit RSRVD RSRVD 20-bit RSRVD 20-bit RSRVD 20-bit RSRVD STATUS STATUS ADDR DATA RSRVD RSRVD Figure 16-4. Bi-directional AC-link Frame with Slot Assignments Figure 28-4 shows Tag and Data Phase organization for the controller and the Codec. The figure also lists the slot definitions that the S3C24A0 AC97 Controller supports. The S3C24A0 AC97 Controller provides synchronization for all data transaction on the AC-link. 16-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 AC97 CONTROLLER S3C24A0 RISC MICROPROCESSOR A data transaction is made up of 256 bits of information broken up into groups of 13 time slots and is called a frame. Time slot 0 is called the Tag Phase and is 16 bits long. The other 12 time slots are called the Data Phase. The Tag Phase contains one bit that identifies a valid frame and 12 bits that identify the time slots in the Data Phase that contain valid data. Each time slot in the Data Phase is 20 bits long. A frame begins when SYNC goes high. The amount of time that SYNC is high corresponds to the Tag Phase. AC97 frames occur at fixed 48 kHz intervals and are synchronous to the 12.288 MHz bit rate clock, BITCLK. The controller and the Codec use the SYNC and BITCLK to determine when to send transmit data and when to sample received data. A transmitter transitions the serial data stream on each rising edge of BITCLK and a receiver samples the serial data stream on falling edges of BITCLK. The transmitter must tag the valid slots in its serial data stream. The valid slots are tagged in slot 0. Serial data on the AC-link is ordered most significant bit (MSB) to least significant bit (LSB). The Tag Phase's first bit is bit 15 and the first bit of each slot in Data Phase is bit 19. The last bit in any slot is bit 0. AC-LINK OUTPUT FRAME (SDATA_OUT) Tag Phase 48KHz Data Phase SYNC AC '97 samples SYNC assertion here AC '97 Controller samples first SDATA_OUT bit of frame here 12.288MHz BIT_CLK SDATA_OUT Valid Frame Slot(1) Slot(2) Slot(12) "0" ID1 ID0 19 0 19 0 END of previous Audio Frame START of Data phase Slot# 1 END of Data Frame Slot# 12 Figure 16-5. AC-link Output Frame 16-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR AC97 CONTROLLER AC-LINK INPUT FRAME (SDATA_IN) Tag Phase Data Phase SYNC AC '97 samples SYNC assertion here AC '97 Controller samples first SDATA_IN bit of frame here BIT_CLK SDATA_OUT Codec Ready Slot(1) Slot(2) Slot(12) "0" "0" "0" 19 0 19 0 END of previous Audio Frame START of Data phase Slot# 1 Figure 16-6. AC-link Input Frame END of Data Frame Slot# 12 16-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 AC97 CONTROLLER S3C24A0 RISC MICROPROCESSOR AC97 POWERDOWN SYNC BIT_CLK SDATA_OUT slot 12 prev.frame TAG Write to 0X26 Data PR4 SDATA_IN slot 12 prev.frame TAG Figure 16-7. AC97 Powerdown Timing Powering Down the AC-link The AC-link signals enter a low power mode when the AC97 Codec Powerdown register (0x26) bit PR4 is set to a 1 (by writing 0x1000). Then the Primary Codec drives both BITCLK and SDATA_IN to a logic low voltage level. The sequence follows the timing diagram shown in Figure 16-7. The AC97 Controller transmits the write to Powerdown register (0x26) over the AC-link. Set up the AC97 Controller so that it does not transmit data to slots 3-12 when it writes to the Powerdown register bit PR4 (data 0x1000), and it does not require the Codec to process other data when it receives a power down request. When the Codec processes the request it immediately transitions BITCLK and SDATA_IN to a logic low level. The AC97 Controller drives SYNC and SDATA_OUT to a logic low level after programming the AC_GLBCTRL register. Waking up the AC-link - Wake Up Triggered by the AC97 Controller AC-link protocol provides for a cold AC97 reset and a warm AC97 reset. The current power-down state ultimately dictates which AC97 reset is used. Registers must stay in the same state during all power-down modes unless a cold AC97 reset is performed. In a cold AC97 reset, the AC97 registers are initialized to their default values. After a power down, the AC-link must wait for a minimum of four audio frame times after the frame in which the power down occurred before it can be reactivated by reasserting the SYNC signal. When AC-link powers up, it indicates readiness through the Codec ready bit (input slot 0, bit 15). 16-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR AC97 CONTROLLER PR0=1 PR1=1 PR2=1 PR4=1 Normal ADCs off PR0 DACs off PR1 Analog off PR2 or PR3 PR2=0 & ANL=1 Digital I/F off PR4 Shut off AC-link PR0=0 & ADC=1 PR1=0 & DAC=1 Warm Reset Ready=1 Default Cold Reset Figure 16-8 AC97 Power down/Power up Flow Cold AC97 Reset A cold reset is generated when the nRESET pin is asserted through the AC_GLBCTRL. Asserting and deasserting nRESET activates BITCLK and SDATA_OUT. All AC97 control registers are initialized to their default power on reset values. nRESET is an asynchronous AC97 input. Warm AC97 Reset A warm AC97 reset reactivates the AC-link without altering the current AC97 register values. A warm reset is generated when BITCLK is absent and SYNC is driven high. In normal audio frames, SYNC is a synchronous AC97 input. When BITCLK is absent, SYNC is treated as an asynchronous input used to generate a warm reset to AC97.The AC97 Controller must not activate BITCLK until it samples SYNC low again. This prevents a new audio frame from being falsely detected; When the AC97 Controller receives a wake-up from the Codec. 16-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 AC97 CONTROLLER S3C24A0 RISC MICROPROCESSOR AC97 CONTROLLER SPECIAL REGISTERS AC97 GLOBAL CONTROL REGISTER (AC_GLBCTRL) Register AC_GLBCTRL Address 0x45000000 R/W R/W Description AC97 Global Control Register Reset Value 0x000000 AC_GLBCTRL Reserved Codec ready interrupt enable PCM out channel underrun interrupt enable PCM in channel overrun interrupt enable Mic in channel overrun interrupt enable PCM out channel threshold interrupt enable PCM in channel threshold interrupt enable MIC in channel threshold interrupt enable Reserved PCM out channel transfer mode PCM in channel transfer mode MIC in channel transfer mode Reserved Transfer data enable using AC-link AC-Link on Warm reset Cold reset Bit [31:23] [22] [21] [20] [19] [18] [17] [16] [15:14] [13:12] [11:10] [9:8] [7:4] [3] [2] [1] [0] Reserved Description 0 : Disable 0 : Disable 1 : Enable ( FIFO is empty) 0 : Disable 1 : Enable ( FIFO is full) 0 : Disable 1 : Enable ( FIFO is full) 0 : Disable 1 : Enable ( FIFO is half empty) 0 : Disable 1 : Enable ( FIFO is half full) 0 : Disable 1 : Enable ( FIFO is half full) Reserved 00 : Off 00 : Off 00 : Off Reserved 0 : Disable 1 : Enable 01 : PIO 01 : PIO 01 : PIO 10 : DMA 10 : DMA 10 : DMA 1 : Enable Initial State 0x00 0 0 0 0 0 0 0 00 11 : Reserved 11 : Reserved 11 : Reserved 00 00 00 0000 0 0 0 0 0 : Off 1 : SYNC signal transfer to Codec 0 : Normal 1 : Wake up codec from power down 0 : Normal 1 : Reset Codec and Controller logic 16-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR AC97 CONTROLLER AC97 GLOBAL STATUS REGISTER (AC_GLBSTAT) Register AC_GLBSTAT Address 0x45000004 R/W R Description AC97 Global Status Register Reset Value 0x00000000 AC_GLBSTAT Reserved Codec ready interrupt PCM out channel underrun interrupt PCM in channel overrun interrupt MIC in channel overrun interrupt PCM out channel threshold interrupt PCM in channel threshold interrupt MIC in channel threshold interrupt Reserved Controller main state Bit [31:23] [22] [21] [20] [19] [18] [17] [16] [15:3] [2:0] Reserved 0 : Not requested 0 : Not requested 0 : Not requested 0 : Not requested 0 : Not requested 0 : Not requested 0 : Not requested Reserved. 000 : Idle 011 : Active Description 1 : Requested 1 : Requested 1 : Requested 1 : Requested 1 : Requested 1 : Requested 1 : Requested Initial State 0x00 0 0 0 0 0 0 0 0x000 001 : Init 100 : LP 010 : Ready 101 : Warm 000 16-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 AC97 CONTROLLER S3C24A0 RISC MICROPROCESSOR AC97 CODEC COMMAND REGISTER (AC_CODEC_CMD) Register AC_CODEC_CMD Address 0x45000008 R/W R/W Description AC97 Codec Command Register Reset Value 0x00000000 AC_CODEC_CMD Reserved Read enable Address Data Bit [31:24] [23] [22:16] [15:0] Reserved 0 : Command write Description 1 : Status read Initial State 0x00 0 0x00 0x0000 Codec command address Codec command data AC97 CODEC STATUS REGISTER (AC_CODEC_STAT) Register AC_CODEC_STAT Address 0x4500000C R/W R Description AC97 Codec Status Register Reset Value 0x00000000 AC_CODEC_STAT Reserved Address Data Bit [31:23] [22:16] [15:0] Reserved. Codec status address Codec status data Description Initial State 0x00 0x00 0x0000 AC97 PCM OUT/IN CHANNEL FIFO ADDRESS REGISTER (AC_PCMADDR) Register AC_PCMADDR Address 0x45000010 R/W R Description AC97 PCM Out/In Channel FIFO Address Register Reset Value 0x00000000 AC_PCMADDR Reserved Out read address Reserved In read address Reserved Out write address Reserved In write address Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Reserved. Description Initial State 0000 0000 0000 0000 0000 0000 0000 0000 PCM out channel FIFO read address Reserved. PCM in channel FIFO read address Reserved. PCM out channel FIFO write address Reserved. PCM in channel FIFO write address 16-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR AC97 CONTROLLER AC97 MIC IN CHANNEL FIFO ADDRESS REGISTER (AC_MICADDR) Register AC_MICADDR Address 0x45000014 R/W R Description AC97 Mic In Channel FIFO Address Register Reset Value 0x00000000 AC_MICADDR Reserved Read address Reserved Write address Bit [31:20] [19:16] [15:4] [3:0] Reserved. Description Initial State 0000 0000 0x000 0000 MIC in channel FIFO read address Reserved. MIC in channel FIFO write address AC97 PCM OUT/IN CHANNEL FIFO DATA REGISTER (AC_PCMDATA) Register AC_PCMDATA Address 0x45000018 R/W R/W Description AC97 PCM Out/In Channel FIFO Data Register Reset Value 0x00000000 AC_PCMDATA Left data Bit [31:16] Description PCM out/in left channel FIFO data Read : PCM in left channel Write : PCM out left channel PCM out/in right channel FIFO data Read : PCM in right channel Write : PCM out right channel Initial State 0x0000 Right data [15:0] 0x0000 AC97 MIC IN CHANNEL FIFO DATA REGISTER (AC_MICDATA) Register AC_MICDATA Address 0x4500001C R/W R/W Description AC97 MIC In Channel FIFO Data Register Reset Value 0x00000000 AC_MICDATA Reserved Mono data Bit [31:16] [15:0] Reserved Description Initial State 0x0000 0x0000 MIC in mono channel FIFO data 16-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 AC97 CONTROLLER S3C24A0 RISC MICROPROCESSOR NOTES 16-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB HOST USB HOST CONTROLLER (Preliminary) OVERVIEW S3C24A0 supports 2 port USB host interface as follows; Open HCI Rev 1.0 compatible. USB Rev1.1 compatible 2 down stream ports. Support for both LowSpeed and HighSpeed USB devices Figure 17-1. USB Host Controller Block Diagram 17-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB HOST S3C24A0 RISC MICROPROCESSOR USB HOST CONTROLLER SPECIAL REGISTERS The S3C24A0 USB Host controller complies with OPEN HCI Rev 1.0. Please refer to Open Host Controller Interface Rev 1.0 specification for detail information. OHCI REGISTERS FOR USB HOST CONTROLLER Register HcRevision HcControl HcCommonStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCuttentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 Base Address 0x41000000 0x41000004 0x41000008 0x4100000c 0x41000010 0x41000014 0x41000018 0x4100001C 0x41000020 0x41000024 0x41000028 0x4100002c 0x41000030 0x41000034 0x41000038 0x4100003c 0x41000040 0x41000044 0x41000048 0x4100004C 0x41000050 0x41000054 0x41000058 R/W root hub group frame counter group memory pointer group Description control and status group Reset Value - 17-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE USB DEVICE OVERVIEW USB device controller is designed to provide a high performance full speed function controller solution with DMA I/F. USB device controller allows bulk transfer with DMA, interrupt transfer and control transfer. The functions are as follows: * Full speed USB device controller compatible with the USB specification version 1.1 * DMA interface for bulk transfer * 5 endpoints with FIFO EP0: 16byte (Register) EP1: 128byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA EP2: 128byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA EP3: 128byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA EP4: 128byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA * Integrated USB Transceiver FEATURE -- Fully compliant with USB Specification Version 1.1 -- Full speed (12Mbps) device -- Integrated USB Transceiver -- Supports control, interrupt and bulk transfer -- 5 endpoints with FIFO: One bi-directional control Endpoint with 16-byte FIFO (EP0) Four bi-directional bulk endpoint with 128-byte FIFO (EP1, EP2, EP3, EP4) -- Supports DMA interface for receive and transmit bulk endpoints. (EP1, EP2, EP3, EP4) -- Independent 128byte receive and transmit FIFO to maximize throughput -- Supports suspend and remote wake-up function 18-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR MC_ADDR[13:0] RT_VM_IN RT_VP_IN RXD RT_VP_OUT RT_VM_OUT RT_UX_OEN MC_DATA_IN[31:0] SIU MC_DATA_OUT[31:0] USB_CLK SYS_CLK SIE MCU & DMA I/F SYS_RESETN MC_WR WR_RDN MC_CSN GFI RT_UXSUSPEND MC_INTR DREQN[3:0] DACKN[3:0] FIFOs Figure 18-1. USB Device Block Diagram 18-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE USB DEVICE SPECIAL REGISTERS This section describes the detail functionality about register set USB Device.. All special function register is byte access or word access. All reserved bit is zero. Common indexed registers depend on INDEX_REG(offset address : 0X178) value. For example if you want to write EP0 CSR register, you must write `0x00' on INDEX_REG before writing IN CSR1 register. All Register must be resettled after Host Reset Signaling. Register Name FUNC_ADDR_REG PWR_REG EP_INT_REG (EP0-EP4) USB_INT_REG EP_INT_EN_REG (EP0-EP4) USB_INT_EN_REG FRAME_NUM1_REG FRAME_NUM2_REG INDEX_REG EP0_FIFO_REG EP1_FIFO_REG EP2_FIFO_REG EP3_FIFO_REG EP4_FIFO_REG EP1_DMA_CON EP1_DMA_UNIT EP1_DMA_FIFO EP1_DMA_TTC_L EP1_DMA_TTC_M EP1_DMA_TTC_H Description NON INDEXED REGISTERS Function address register Power management register Endpoint interrupt register USB interrupt register Endpoint interrupt enable register USB Interrupt enable register Frame number 1 register Frame number 2 register Index register Endpoint0 FIFO register Endpoint1 FIFO register Endpoint2 FIFO register Endpoint3 FIFO register Endpoint4 FIFO register Endpoint1 DMA control register Endpoint1 DMA Unit counter register Endpoint1 DMA FIFO counter register Endpoint1 DMA Transfer counter low-byte register Endpoint1 DMA Transfer counter middle-byte register Endpoint1 DMA Transfer counter high-byte register Offset Address 0x140 0x144 0x148 0x158 0x15C 0x16C 0x170 0x174 0x178 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x200 0x204 0x208 0x20C 0x210 0x214 18-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR EP2_DMA_CON EP2_DMA_UNIT EP2_DMA_FIFO EP2_DMA_TTC_L EP2_DMA_TTC_M EP2_DMA_TTC_H EP3_DMA_CON EP3_DMA_UNIT EP3_DMA_FIFO EP3_DMA_TTC_L EP3_DMA_TTC_M EP3_DMA_TTC_H EP4_DMA_CON EP4_DMA_UNIT EP4_DMA_FIFO EP4_DMA_TTC_L EP4_DMA_TTC_M EP4_DMA_TTC_H MAXP_REG IN INDEXED REGISTERS IN_CSR1_REG IN_CSR2_REG OUT INDEXED REGISTERS OUT_CSR1_REG OUT_CSR2_REG OUT_FIFO_CNT1_REG OUT_FIFO_CNT2_REG Endpoint2 DMA control register Endpoint2 DMA Unit counter register Endpoint2 DMA FIFO counter register Endpoint2 DMA Transfer counter low-byte register Endpoint2 DMA Transfer counter middle-byte register Endpoint2 DMA Transfer counter high-byte register Endpoint3 DMA control register Endpoint3 DMA Unit counter register Endpoint3 DMA FIFO counter register Endpoint3 DMA Transfer counter low-byte register Endpoint3 DMA Transfer counter middle-byte register Endpoint3 DMA Transfer counter high-byte register Endpoint4 DMA control register Endpoint4 DMA Unit counter register Endpoint4 DMA FIFO counter register Endpoint4 DMA Transfer counter low-byte register Endpoint4 DMA Transfer counter middle-byte register Endpoint4 DMA Transfer counter high-byte register Endpoint MAX Packet register EP In Control status register 1 EP In Control status register 2 EP Out Control status register 1 EP Out Control status register 2 EP Out Write count register 1 EP Out Write count register 2 0x218 0x21C 0x220 0x224 0x228 0x22C 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x180 0x184 0x188 0x190 0x194 0x198 0x19C COMMON INDEXED REGISTERS 18-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE FUNC_ADDR_REG This register maintains the USB Device Address assigned by the host. The MCU writes the value received through a SET_ADDRESS descriptor to this register. This address is used for the next token. Register FUNC_ADDR_REG Address 0x44A00140 R/W R/W (byte) Description Function address register Reset Value 0x00 FUNC_ADDR_RE G ADDR_UPDATE Bit [7] MCU R/W USB R /CLEAR Description The MCU sets this bit whenever it updates the FUNCTION_ADDR field in this register. This bit will be cleared by USB when DATA_END bit in EP0_CSR register. The MCU write the unique address, assigned by host, to this field. Initial State 0 FUNCTION_ADDR [6:0] R/W R 00 18-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR POWER MANAGEMENT REGISTER (PWR_REG) This register is power control register in USB block. Register PWR_REG Address 0x44A00144 R/W R/W (byte) Description Power management register Reset Value 0x00 FUNC_ADDR Reserved ISO_UPDATE Bit [31:9] [7] MCU USB Reserved Description Initial State 0 0 R/W R Used for ISO mode only. If set, GFI waits for a SOF token to set IN_PKT_RDY even though a packet to send is already loaded by MCU. If an IN token is received before a SOF token, then a zero length data packet will be sent. Reserved The USB sets this bit if reset signaling is received from the host. This bit remains set as long as reset signaling persists on the bus The MCU sets this bit for MCU resume. The USB generates the resume signaling depending RESUME CON Register, while this bit is set in suspend mode. This bit can be set by USB, automatically when the device enter into suspend mode. It is cleared under the following conditions 1) The MCU clears the MCU_RESUME bit by writing `0', to end remote resume signaling. 2) The resume signal form host is received. Suspend mode enable control bit 0 = Disable(default). The device will not enter suspend mode. 1 = Enable suspend mode Reserved USB_RESET [6:4] [3] R SET 0 MCU_RESUME [2] R/W R /CLEAR SUSPEND_MODE [1] R SET /CLEAR 0 SUSPEND_EN [0] R/W R 0 18-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE INTERRUPT REGISTER (EP_INT_REG, USB_INT_REG) The USB core has two interrupt registers. These registers act as status registers for the MCU when it is interrupted. The bits are cleared by writing a `1'(not `0') to each bit that was set. Once the MCU is interrupted, MCU should read the contents of interrupt-related registers and write back to clear the contents if it is necessary. Register EP_INT_REG Address 0x44A00148 R/W R/W (byte) Description EP Interrupt pending/clear register Reset Value 0x00 EP_INT_REG EP1~EP4 Interrupt Bit [4:1] MCU R /CLEAR USB SET Description For BULK/INTERRUPT IN endpoints: The USB sets this bit under the following conditions: 1. IN_PKT_RDY bit is cleared. 2. FIFO is flushed 3. SENT_STALL set. For BULK/INTERRUPT OUT endpoints: USB sets this bit under the following conditions: 1. Sets OUT_PKT_RDY bit 2. Sets SENT_STALL bit For ISO IN endpoints: the USB sets this bit under the following conditions: 1. UNDER_RUN bit is set 2. IN_PKT_RDY bit is cleared. 3. FIFO is flushed Note: conditions 1 and 2 are mutually exclusive For ISO OUT endpoints: USB sets this bit under the following conditions: 1. OUT_PKT_RDY bit is set 2. OVER RUN bit is set. Note: Conditions 1 and 2 are mutually exclusive. Initial State 0 EP0 Interrupt [0] R /CLEAR SET This bit corresponds to endpoint 0 interrupt The USB sets this bit under the following conditions: 1. OUT_PKT_RDY bit is set. 2. IN_PKT_RDY bit is cleared. 3. SENT_STALL bit is set 4. SETUP_END bit is set 5. DATA_END bit is cleared(Indicates end of control transfer) 0 18-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR Register USB_INT_REG Address 0x44A00158 R/W R/W (byte) Description USB Interrupt pending/clear register Reset Value 0x00 USB_INT_REG RESET Interrupt RESUME Interrupt Bit [2] [1] MCU R /CLEAR R /CLEAR USB SET SET Description The USB set this bit, when it receives reset signaling. The USB sets this bit, when it receives resume signaling, while in suspend mode. If the resume is due to a USB reset, then the MCU is first interrupted with a RESUME interrupt. Once the clocks resume and the SE0 condition persists for 3ms, USB RESET interrupt will be asserted. The USB sets this bit when it receives suspend signalizing. This bit is set whenever there is no activity for 3ms on the bus. Thus, if the MCU does not stop the clock after the first suspend interrupt, it will be continue to be interrupted every 3ms as long as there is no activity on the USB bus. By default this interrupt is disabled. Initial State 0 0 SUSPEND Interrupt [0] R /CLEAR SET 0 18-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE INTERRUPT ENABLE REGISTER (EP_INT_EN_REG, USB_INT_REG) Corresponding to each interrupt register, there is an INTERRUPT ENABLE register (except resume interrupt enable). By default usb reset interrupt is enabled. If bit = 0, the interrupt is disabled If bit = 1, the interrupt is enabled Register EP_INT_EN_REG Address 0x44A0015C R/W R/W (byte) Description Determines which interrupt is enabled. Reset Value 0xFF INT_MASK_REG EP4_INT_EN EP3_INT_EN EP2_INT_EN EP1_INT_EN EP0_INT_EN Bit [4] [3] [2] [1] [0] MCU R/W R/W R/W R/W R/W USB R R R R R Description EP4 Interrupt Enable bit 0 = Interrupt disable EP3 Interrupt Enable bit 0 = Interrupt disable EP2 Interrupt Enable bit 0 = Interrupt disable EP1 Interrupt Enable bit 0 = Interrupt disable EP0 Interrupt Enable bit 0 = Interrupt disable Initial State 1 1 = Enable 1 1 = Enable 1 1 = Enable 1 1 = Enable 1 1 = Enable 18-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR Register USB_INT_EN_REG Address 0x44A0016C R/W R/W (byte) Description Determines which interrupt is enabled. Reset Value 0x04 INT_MASK_REG RESET_INT_EN Reserved SUSPEND_INT_EN Bit [2] [1] [0] MCU R/W R/W USB R R Description Reset interrupt enable bit 0 = Interrupt disable 1 = Enable Suspend interrupt enable bit 0 = Interrupt disable 1 = Enable Initial State 1 0 0 18-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE FRAME NUMBER REGISTER (FPAME_NUM1_REG, FRAME_NUM2_REG) When host transfer USB packet, there is frame number in SOF(Start Of Frame). The USB catch this frame number and load it into this register, automatically. Register FRAME_NUM1_REG Address 0x44A00170 R/W R (byte) Description Frame number lower byte register Reset Value 0x00 FRAME_NUM_REG FRAME_NUM1 Bit [7:0] MCU R USB W Description Frame number lower byte value Initial State 00 Register FRAME_NUM2_REG Address 0x44A00174 R/W R (byte) Description Frame number higher byte register Reset Value 0x00 FRAME_NUM_REG FRAME_NUM2 Bit [7:0] MCU R USB W Description Frame number higher byte value Initial State 00 18-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR INDEX REGISTER (INDEX_REG) This INDEX register is used to indicate certain endpoint registers effectively. MCU can access the endpoint registers(MAXP_REG,IN_CSR1_REG,IN_CSR2_REG,OUT_CSR1_REG,OUT_CSR2_REG,OUT_FIFO_CNT1_ REG,OUT_FIFO_CNT2_REG) for an endpoint inside the core using the INDEX register. Register INDEX_REG Address 0x44A00178 R/W R/W (byte) Description Register index register Reset Value 0x00 INDEX_REG INDEX Bit [7:0] MCU R/W USB R Description It indicates a certain endpoint. Initial State 00 18-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE END POINT0 CONTROL STATUS REGISTER (EP0_CSR) This register has the control and status bits for Endpoint 0. Since a control transaction involves both IN and OUT tokens, there is only one CSR register, mapped to the IN CSR1 register. (share IN1_CSR and can access by writing index register "0" and read/write IN1_CSR) Register EP0_CSR Address 0x44A00184 R/W R/W (byte) USB CLEAR CLEAR CLEAR Description Endpoint 0 status register Reset Value 0x00 EP0_CSR SERVICED_SE TUP_END SERVICED_OU T_PKT_RDY SEND_STALL Bit [7] [6] [5] MCU W W R/W Description The MCU should write a "1" to this bit to clear SETUP_END The MCU should write a "1" to this bit to clear OUT_PKT_RDY MCU should writes a "1" to this bit at the same time it clears OUT_PKT_RDY, if it decodes an invalid token. 0 = Finish the STALL condition 1 = The USB issues a STALL and shake to the current control transfer. The USB sets this bit when a control transfer ends before DATA_END is set. When the USB sets this bit, an interrupt is generated to the MCU. When such a condition occurs, the USB flushes the FIFO and invalidates MCU access to the FIFO. The MCU sets this bit below conditions: 1. After loading the last packet of data into the FIFO, at the same time IN_PKT_RDY is set. 2. While it clears OUT_PKT_RDY after unloading the last packet of data. 3. For a zero length data phase. The USB sets this bit if a control transaction is stopped due to a protocol violation. An interrupt is generated when this bit is set. The MCU should write "0" to clear this bit. The MCU sets this bit after writing a packet of data into EP0 FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated when the USB clears this bit, so as the MCU to load the next packet. For a zero length data phase, the MCU sets DATA_END at the same time. The USB sets this bit once a valid token is written to the FIFO. An interrupt is generated when the USB sets this bit. The MCU clears this bit by writing a "1" to the SERVICED_OUT_PKT_RDY bit. Initial State 0 0 0 SETUP_END [4] R SET 0 DATA_END [3] SET CLEAR 0 SENT_STALL [2] CLE AR SET SET 0 IN_PKT_RDY [1] CLEAR 0 OUT_PKT_RDY [0] R SET 0 18-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG, IN_CSR2_REG) Register IN_CSR1_REG Address 0x44A00184 R/W R/W (byte) USB R/ CLEAR This bit can be used in Set-up procedure. 0 : There are alternation of DATA0 and DATA1 1 : The data toggle bit is cleared and PID in packet will maintain DATA0 The USB sets this bit when an IN token issues a STALL handshake, after the MCU sets SEND_STALL bit to start STALL handshaking. When the USB issues a STALL handshake, IN_PKT_RDY is cleared 0 : The MCU clears this bit to finish the STALL condition. 1 : The MCU issues a STALL handshake to the USB. The MCU sets this bit if it intends to flush the packet in Input-related FIFO. This bit is cleared by the USB when the FIFO is flushed. The MCU is interrupted when this happens. If a token is in process, the USB waits until the transmission is complete before FIFO flushing. If two packets are loaded into the FIFO, only first packet (The packet is intended to be sent to the host) is flushed, and the corresponding IN_PKT_RDY bit is cleared Valid For Iso Mode Only The USB sets this bit when in ISO mode, an IN token is received and the IN_PKT_RDY bit is not set. The USB sends a zero length data packet for such conditions, and the next packet that is loaded into the FIFO is flushed. This bit is cleared by writing 0. The MCU sets this bit, after writing a packet of data into the FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated when te USB clears this bit, so the MCU can load the next packet. While this bit is set, the MCU will not be able to write to the FIFO. If the SEND STALL bit is set by the MCU, this bit cannot be set. Description IN END POINT control status register1 Reset Value 0x00 IN_CSR1_REG Reserved CLR_DATA_ TOGGLE Bit [7] [6] MCU R/W Description Initial State 0 0 SENT_STALL [5] R/ CLEAR SET 0 SEND_STALL [4] W/R R 0 FIFO_FLUSH [3] W/ CLEAR CLEAR 0 UNDER_RUN [2] R/ CLEAR Set 0 Reserved IN_PKT_RDY [1] [0 R/SET CLEAR 0 0 18-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE Register IN_CSR2_REG Address 0x44A00188 R/W R/W (byte) USB R Description IN END POINT control status register2 Reset Value 0x20 IN_CSR1_REG AUTO_SET Bit [7] MCU R/W Description If set, whenever the MCU writes MAXP data, IN_PKT_RDY will automatically be set by the core, without any intervention from MCU. If the MCU writes less than MAXP data, then IN_PKT_RDY bit has to be set by the MCU. This bit is used only for endpoints whose transfer type is programmable. '1' Configures endpoint to ISO mode '0' Configures endpoint to Bulk mode This bit is used only for endpoints whose direction is programmable. '1' Configures Endpoint Direction as IN '0' Configures Endpoint Direction as OUT This bit determines whether the interrupt should be issued, or not, when the EP1 IN_PKT_RDY condition happens. This is only useful for DMA mode. 0 = Interrupt enable, 1 = Interrupt Disable Initial State 0 ISO [6] R/W R 0 MODE_IN [5] R/W R 1 IN_DMA_INT_EN [4] R/W R 0 18-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR END POINT OUT CONTROL STATUS REGISTER(OUT_CSR1_REG, OUT_CSR2_REG) Register OUT_CSR1_REG Address 0x44A00190 R/W R/W (byte) USB CLEAR SET Description End Point out control status register1 Reset Value 0x00 OUT_CSR1_REG CLR_DATA_TOGGLE SENT_STALL Bit [7] [6] MCU R/W CLEAR /R Description When the MCU writes a 1 to this bit, the data toggle sequence bit is reset to DATA0. The USB sets this bit when an OUT token is ended with a STALL handshake. The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT TOKEN. 0 : The MCU clears this bit to end the STALL condition handshake, IN PKT RDY is cleared. 1 : The MCU issues a STALL handshake to the USB. The MCU clears this bit to end the STALL condition handshake, IN PKT RDY is cleared. The MCU write a 1 to flush the FIFO. This bit can be set only when OUT_PKT_RDY (D0) is set. The packet due to be unloaded by the MCU will be flushed. This bit is valid only in ISO mode. This bit should be sampled with OUT_PKT_RDY . When set, it indicates the data packet due to be unloaded by the MCU has an error (either bit stuffing or CRC). If two packets are loaded into the FIFO, and the second packet has an error, then this bit gets set only after the first packet is unloaded. This bit is automatically cleared when OUT_PKT_RDY gets cleared. Initial State 0 0 SEND_STALL [5] R/W R 0 FIFO_FLUSH [4] R/W CLEAR 0 DATA_ERROR [3] R R/W 0 OVER_RUN [2] R/Clear R/W This bit is valid only in ISO mode. This bit is set if the core is not able to load an OUT ISO token into the FIFO. MCU clears this bit by writing 0. The USB sets this bit after it has loaded a packet of data into the FIFO. Once the MCU reads the packet from FIFO, this bit should be cleared by MCU. (Write a "0") 0 Reserved OUT_PKT_RDY [1] [0] R/ CLEAR SET 0 0 18-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE Register OUT_CSR2_REG Address 0x44A00194 R/W R/W (byte) USB R Description End Point out control status register2 Reset Value 0x00 OUT_CSR2_REG AUTO_CLR Bit [7] MCU R/W Description If MCU set, whenever the MCU reads data from the OUT FIFO, OUT_PKT_RDY will automatically be cleared by the logic, without any intervention from MCU. This bit determines endpoint transfer type. '0' : Configures endpoint to Bulk mode. '1' : Configures endpoint to ISO mode This bit determines whether the interrupt should be issued, or not. OUT_PKT_RDY condition happens. This is only useful for DMA mode 0 = Interrupt Enaebl 1 = Interrupt Disable Initial State 0 ISO [6] R/W R 0 OUT_DMA_INT_EN [5] R/W R 0 18-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR END POINT FIFO REGISTER (EPN_FIFO_REG) To access EPn FIFO, the MCU should access EPn_FIFO_REG. Register EP0_FIFO EP1_FIFO EP2_FIFO EP3_FIFO EP4_FIFO Address 0x44A001C0 0x44A001C4 0x44A001C8 0x44A001CC 0x44A001D0 R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description End Point0 FIFO register End Point1 FIFO register End Point2 FIFO register End Point3 FIFO register End Point4 FIFO register Reset Value 0xXX 0xXX 0xXX 0xXX 0xXX EPn_FIFO FIFO_DATA Bit [7:0] MCU R/W USB R/W Description FIFO data value Initial State 0xXX 18-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE MAX PACKET REGISTER (MAXP_REG) Register MAXP_REG Address 0x44A00180 R/W R/W (byte) Description End Point MAX packet register Reset Value 0x01 MAXP_REG MAXP Bit [3:0] MCU R/W USB R Description 0000 : Reserved 0001 : MAXP = 8 Byte 0010 : MAXP = 16 Byte 0100 : MAXP = 32 Byte 1000 : MAXP = 64 Byte Initial State 0001 18-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR END POINT OUT WRITE COUNT REGISTER(OUT_FIFO_CNT1_REG, OUT_FIFO_CNT2_REG) These registers maintain the number of bytes in the packet due to be unloaded by the MCU. Register OUT_FIFO_CNT1_REG Address 0x44A00198 R/W R (byte) Description End Point out write count register1 Reset Value 0x00 OUT_FIFO_CNT1_REG OUT_CNT_LOW Bit [7:0] MCU R USB W Description Lower byte of write count Initial State 00 Register OUT_FIFO_CNT2_REG Address 0x44A0019C R/W R (byte) Description End Point out write count register2 Reset Value 0x00 OUT_FIFO_CNT2_REG OUT_CNT_HIGH Bit [7:0] MCU R USB W Description Higher byte of write count Initial State 00 18-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE DMA INTERFACE CONTROL REGISTER (EPN_DMA_CON) Register EP1_DMA_CON EP2_DMA_CON EP3_DMA_CON EP4_DMA_CON Address 0x44A00200 0x44A00218 0x44A00240 0x44A00258 R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA interface control register EP2 DMA interface control register EP3 DMA interface control register EP4 DMA interface control register Reset Value 0x00 0x00 0x00 0x00 EPn_DMA_CON IN_RUN_OB STATE DEMAND_MODE Bit [7] [6:4] [3] MCU R R R/W USB W W R Description IN DMA Run Observation DMA State Monitoring DMA Demand mode enable bit '0' : Demand mode disable '1' : Demand mode enable This bit function is separated write and read operation Write operation: `0' = Stop `1' = Run Read operation: OUT DMA Run Observation This bit is used to start DMA operation 0 = Stop 1 = Run This bit is used to set DMA mode 0 = Interrupt Mode 1 = DMA Mode Initial State 0 0 0 OUT_RUN_OB / OUT_DMA_RUN [2] R/W R/W 0 IN_DMA_RUN DMA_MODE_EN [1] [0] R/W R/W R R 0 0 18-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR DMA UNIT COUNTER REGISTER (EPN_DMA_UNIT) This register is valid in demand mode. In case not demand mode, this register value must be set `0x01' Register EP1_DMA_UNIT EP2_DMA_UNIT EP3_DMA_UNIT EP4_DMA_UNIT Address 0x44A00204 0x44A0021C 0x44A00244 0x44A0025C R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA transfer unit counter base register EP2 DMA transfer unit counter base register EP3 DMA transfer unit counter base register EP4 DMA transfer unit counter base register Reset Value 0x00 0x00 0x00 0x00 DMA_UNIT EPn_UNIT_CNT Bit [7:0] MCU R/W USB R Description EP DMA transfer unit counter value Initial State 0x00 18-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR USB DEVICE DMA FIFO COUNTER REGISTER (EPN_DMA_FIFO) This register has byte size in FIFO to be transferred by DMA. In case OUT_DMA_RUN enable, the value in OUT FIFO Write Count Register1 will be loaded in this register automatically. In case of IN DMA Mode, the MCU should set proper value by S/W. Register EP1_DMA_FIFO EP2_DMA_FIFO EP3_DMA_FIFO EP4_DMA_FIFO Address 0x44A00208 0x44A00220 0x44A00248 0x44A00260 R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA transfer FIFO counter base register EP2 DMA transfer FIFO counter base register EP3 DMA transfer FIFO counter base register EP4 DMA transfer FIFO counter base register Reset Value 0x00 0x00 0x00 0x00 DMA_FIFO EPn_FIFO_CNT Bit [7:0] MCU R/W USB R Description EP DMA transfer FIFO counter value Initial State 0x00 18-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 USB DEVICE S3C24A0 RISC MICROPROCESSOR DMA TOTAL TRANSFER COUNTER REGISTER (EPN_DMA_TTC_L, EPN_DMA_TTC_M, EPN_DMA_TTC_H) This register should have total number of bytes to be transferred using DMA.(Total 24bit Counter) Register EP1_DMA_TTC_L EP1_DMA_TTC_M EP1_DMA_TTC_H EP2_DMA_TTC_L EP2_DMA_TTC_M EP2_DMA_TTC_H EP3_DMA_TTC_L EP3_DMA_TTC_M EP3_DMA_TTC_H EP4_DMA_TTC_L EP4_DMA_TTC_M EP4_DMA_TTC_H Address 0x44A0020C 0x44A00210 0x44A00214 0x44A00224 0x44A00228 0x44A0022C 0x44A0024C 0x44A00250 0x44A00254 0x44A00264 0x44A00268 0x44A0026C R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA total transfer counter(lower byte) EP1 DMA total transfer counter(middle byte) EP1 DMA total transfer counter(higher byte) EP2 DMA total transfer counter(lower byte) EP2 DMA total transfer counter(middle byte) EP2 DMA total transfer counter(higher byte) EP3 DMA total transfer counter(lower byte) EP3 DMA total transfer counter(middle byte) EP3 DMA total transfer counter(higher byte) EP4 DMA total transfer counter(lower byte) EP4 DMA total transfer counter(middle byte) EP4 DMA total transfer counter(higher byte) Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 DMA_TX EPn_TTC_L EPn_TTC_M EPn_TTC_H Bit [7:0] [7:0] [7:0] MCU R/W R/W R/W USB R R R Description DMA total transfer count value(lower byte) DMA total transfer count value(middle byte) DMA total transfer count value(higher byte) Initial State 0x00 0x00 0x00 18-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MODEM INTERFACE MODEM INTERFACE (PRELIMINARY) OVERVIEW This specification defines the interface between the Base-band Modem and the Application Processor for the data-exchange of these two devices (refer Figure 19-1). For the data-exchange, the AP (Application Processor, S3C24A0) has a dual-ported SRAM buffer (on-chip) and the Modem chip can access that SRAM buffer using a typical asynchronous-SRAM interface. Typically, the size of the SRAM buffer is 2KB. For the buffer status and Interrupt Requests, this specification also specifies a few of pre-defined special addresses. The Modem chip can write data in the data buffer and write interrupt control-data to the interrupt-port address for the interrupt request to the AP. The AP reads that data when an interrupt request is accepted and the interrupt is cleared when the AP accesses the interrupt-port address. In the same manner, the AP can write data in the data buffer and write interrupt control-data to the interrupt-port address for the interrupt request to the Modem chip. Address & Control signals Application Processor (S3C24A0) internal SRAM buffer embedded uP Modem chip Data Interrupt request Interrupt request to uP Figure 19-1 Modem interface overview 19-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MODEM INTERFACE S3C24A0 RISC MICROPROCESSOR FEATURES -- 8-bit parallel bus for data transfer -- 2K bytes internal SRAM buffer -- Interrupt request for data exchange -- Programmable interrupt port address 19-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MODEM INTERFACE HARDWARE INTERFACE The Modem chip can access using an external memory interface (for example external SRAM). In this specification, the Modem chip can access the internal SRAM and special address ports of the AP using the 8-bit data-bus and the 2K-byte address-space (i.e. 8-bit data-bus and 11-bit address bus). SIGNAL DESCRIPTION Name XmiIRQn XmiDATA [7:0] XmiADR[10:0] XmiCSn XmiWEn I/O1) O B I I I Active L L L Description Interrupt request to the Modem chip Data bus, driven by the Modem chip Address bus, driven by the Modem chip Chip select, driven by the Modem chip Write enable, driven by the Modem chip XmiOEn I L Read enable, driven by the Modem chip Note 1) I/O direction is on the AP side. I : input O : output B : bi-direction Table 19-1 Modem interface signal description INTERRUPT PORTS Interrupts are requested or cleared if the Modem chip or the AP accesses the interrupt-port (predefined special addresses). That special addresses can be configured by the AP and the default address-map is shown in the Table19-2. Address1) 0x7FE 0x7FF An Interrupt is requested, when the Modem chip writes the AP writes The Interrupt is cleared, when See note 22) the Modem chip reads Note 1) This address is default value. It can be set to the other value by the SFR. Note 2) The interrupt is cleared by the interrupt controller of S3C24A0 Table 19-2 Interrupt ports and interrupt-request/clear conditions Modem chip or AP(S3C24A0) can read the data that indicates what event happens - data transfer requested, data transfer done, special command issued, etc. - from interrupt port address. That data format should be defined for communication between the modem chip and AP. 19-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MODEM INTERFACE S3C24A0 RISC MICROPROCESSOR ADDRESS MAPPING Address map of 24A0 (word) Modem (byte) 0x000 0x001 0x002 0x003 Buffer (word) 0x000 0x004 0x008 0x00C 0x41100000 0x41100004 0x41100008 0x4110000C 2K Bytes buffer area 0x7FC 0x7FD 0x7FE 0x7FF modem interface area 0x7FC 0x411007FC 0x41180000 0x41180004 SFR Figure 19-2 Modem interface address mapping 19-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MODEM INTERFACE TIMING DIAGRAM tAVWR XmiADR tCSVWR XmiCSn tAWR XmiWEn tWR tDSUWR XmiDATA tDHWR Figure 19-3 Modem interface write timing diagram Parameter tAVWR tCSVWR tAWR tWR tDSUWR tDHWR Description Address valid to address invalid Chip select active Address valid to write active Write active Write data setup Write data hold Min (ns) 11 ns 11 ns 2 ns 5 ns 3 ns 4 ns Max (ns) - Notes Table 19-3 Modem interface write timing 19-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MODEM INTERFACE S3C24A0 RISC MICROPROCESSOR tAVRD XmiADR tCSVRD XmiCSn tADH tRD XmiOEn tRDDV XmiDATA tRDH tACSDV Figure 19-4 Modem interface read timing diagram Parameter tAVRD tADH tCSVRD tRD tRDDV tRDH tACSDV Description Address valid to address invalid Address hold Chip select active Read active Read active to data valid Read data hold Address and chip select active to data valid Min 20 ns 2.5 ns 17.5 ns 17 ns 4 ns - Max 11.5 ns 12 ns Notes Note ) Output load is 30pF at room temperature (25C) Table 19-4 Modem interface read timing 19-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MODEM INTERFACE SOFTWARE INTERFACE This modem interface provides a generic data-exchange method. This interface does not implement any other complex features except for the interrupt-request/clear such as automatic FIFO managements, etc. The software should be responsible for all other required functionalities for the data exchange between the modem chip and the AP such as the data exchange protocol, the data buffer managements, and etc. MODEM INTERFACE SPECIAL REGISTERS INTERRUPT REQUEST TO AP REGISTER (INT2AP) Register INT2AP Address 0x41180000 R/W R/W Description Interrupt request to AP Register Reset Value 0x000007FE INT2AP Reserved INT2AP_ADR Bit [31:11] Reserved [10:0] Description Modem interface requests the interrupt to AP when modem chip writes this address. This interrupt is cleared by the interrupt controller of AP. Initial State 0 7FE INTERRUPT REQUEST TO MODEM REGISTER (INT2MDM) Register INT2MDM Address 0x41180004 R/W R/W Description Interrupt request to modem Register Reset Value 0x000007FF INT2MDM Reserved INT2MDM_ADR Bit [31:11] Reserved [10:0] Description Initial State 0 Modem interface requests the interrupt to modem chip when AP 7FF writes this address and clears the interrupt when modem chip reads this address. Note ) It is recommended that AP writes data with byte access on the interrupt port because AP can overwrite the data in INT2AP if there are INT2AP and INT2MDM sharing the same word. 19-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MODEM INTERFACE S3C24A0 RISC MICROPROCESSOR NOTES 19-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS GENERAL PURPOSE I/O PORTS (Preliminary) OVERVIEW The S3C24A0 has 32 multi-functional general-purpose input/output port pins (GPIO). Each port can be easily configured by software to meet various system configuration and design requirements. You have to define which function of each pin is used before starting the main program. If the multiplexed functions on a pin are not used, the pin can be configured as I/O ports. The GPIO module in the S3C24A0 has control-registers to configure the power-saving features for the whole chip interface. For example, it contains the control registers for the pin-status of the S3C24A0 that is in the SLEEP state (the SLEEP state is the state that the power source for the whole chip is off except for the powermanagement circuitry). For the normal mode operation, the GPIO pins can be fully configured as an input port with or without pull-up register, an output port, a specific functional pin or an External Interrupt source. 20-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR Table 20-1. S3C24A0 Port Configuration Overview Port GP31 GP30 GP29 GP28 GP27 GP26 GP25 GP24 GP23 GP22 GP21 GP20 GP19 GP18 GP17 GP16 GP15 GP14 GP13 GP12 GP11 GP10 GP9 GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 Selectable Pin Functions (Refers the GPIO port configuration registers - GPCON_U, GPCON_M & GPCON_L.) Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output XuRXD1 XuTXD1 XuRTSn1 XuCTSn1 EXTDMA_ACK1 EXTDMA_ACK0 EXTDMA_REQ1 EXTDMA_REQ0 PWM_TOUT3 PWM_TOUT2 PWM_TOUT1 PWM_TOUT0 PWM_ECLK EINT18 EINT17 EINT16 EINT15 EINT14 EINT13 EINT12 EINT11 Reserved EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 IrDA_RXD IrDA_TXD IrDA_SDBW RTC_ALMINT XkpCOL4 XkpCOL3 XkpCOL2 XkpCOL1 XkpCOL0 XkpROW4 XkpROW3 XkpROW2 XkpROW1 XkpROW0 XspiCLK XspiMISO XspiMOSI RTC_ALMINT Reserved Reserved Reserved Reserved EXTDMA_ACK1 EXTDMA_ACK0 EXTDMA_REQ1 EXTDMA_REQ0 PWM_TOUT3 PWM_TOUT2 PWM_TOUT1 PWM_TOUT0 PWM_ECLK - 20-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS PORT CONTROL DESCRIPTIONS GPIO PORT CONFIGURATION REGISTER FOR NORMAL MODE (GPCON_U, GPCON_M, GPCON_L) In the S3C24A0, 32 pins are multiplexed pins. So, It is determined which function is selected for each pins. The PCON (port control register) determines which function is used for each pin. If GP0 - GP9 are used for the wakeup signal in power down mode, these ports must be configured as an interrupt mode. The wake-up events are generated when the individual GPIO pin is configured as an external interrupt mode regardless of the interrupt mask bits. GPIO PORT DATA REGISTER FOR NORMAL MODE (GPDAT) If Ports are configured as output ports, data can be written to the corresponding bit of GPDAT. If Ports are configured as input ports, the data can be read from the corresponding bit of GPDAT. GPIO PORT PULL-PU CONTROL REGISTER FOR NORMAL MODE (GPPU) The port pull-up register controls the pull-up resister enable/disable of each port group. When the corresponding bit is 0, the pull-up resister of the pin is enabled. When 1, the pull-up resister is disabled. If the port pull-up register is enabled then the pull-up resisters work without pin's functional setting (input, output, EINTn and etc) EXTERNAL INTERRUPT CONTROL REGISTER (EXTINTCn/ EINTFLTn/ EINTMASK/ EINTPEND) The 18 EINT ports are requested by various signaling methods. The EXTINTC register configures the signaling method among the low level trigger, high level trigger, falling edge trigger, rising edge trigger, and both edge trigger for the external interrupt request All 18 EINT ports generate an interrupt when each port is configured as the interrupt mode and the corresponding interrupt is unmasked. However, even if the interrupt is masked to a corresponding interrupt port (EINTMASK), an interrupt pending bit (EINTPEND) is set when the port is configured as the interrupt mode. The 8 EINT ports have a digital filter. (Refer to EINTFLTn register) Only 10 EINT ports (EINT [9:0]) are used for wake-up sources. In the SLEEP mode, all wake-up sources are disabled when the nBATFLT signal is asserted to low (it will not generate a wake-up event nor a interrupt is pending). Wake-up source is updated in EINTPEND including RTC alarm wake-up bit. PERIPHERAL PORT PULL-UP CONTROL REGISTER FOR NORMAL MODE (PERIPU) The peripheral port pull-up control register controls internal pull-up resister attached to the corresponding port pin. When the corresponding bit is 0, the pull-up resister of the pin is enabled. When 1, the pull-up resister is disabled. ALIVE CONTROL REGISTER (ALIVECON) These bits notify what kind of reset occurred and Battery fault has occurred or not. 20-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR GPIO OUTPUT DATA REGISTER FOR SLEEP MODE (GPDAT_SLEEP) GPIO port output data register in sleep mode. In sleep mode the value of GPDAT is meaningless. GPIO OUTPUT CONTROL REGISTER FOR SLEEP MODE (GPOEN_SLEEP) GPIO port output control register for each port in sleep mode. In sleep mode the value of GPCON is meaningless. GPIO PULL-UP CONTROL REGISTER FOR SLEEP MODE (GPPU_SLEEP) Control pull up resister attached to the corresponding GPIO port pin in sleep mode. In sleep mode the value of GPPU is meaningless. PERIPHERAL PORT OUTPUT DATA REGISTER FOR SLEEP MODE (PERIDAT_SLEEPn) Peripheral port output data register in sleep mode. PERIPHERAL PORT OUTPUT CONTROL REGISTER FOR SLEEP MODE (PERIOEN_SLEEPn) Peripheral port output control register for each port in sleep mode. PERIPHERAL PORT PULL-UP CONTROL REGISTER FOR SLEEP MODE (PERIPU_SLEEP) Control pull up resister attached to the peripheral port in sleep mode. In sleep mode the value of PERIPU is meaningless. RESET COUNT COMPARE REGISTER (RSTCNT) These value control the duration of reset when wake-up from sleep mode. GENERAL PURPOSE RAM ARRAY (GPRAMn) General purpose RAM array, 16 x 32 bit. 20-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS I/O PORT CONTROL REGISTER GPIO UPPER PORT CONTROL REGISTER (GPCON_U) Register GPCON_U Address 0x44800000 R/W R/W Description Configures the pins of upper ports[31:19] Reset Value 0x0 GPCON_U GP31 GP30 GP29 GP28 GP27 GP26 GP25 GP24 GP23 GP22 GP21 GP20 GP19 Bit [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = XuRXD1 00 = Input 10 = XuTXD1 00 = Input 10 = XuRTSn1 00 = Input 10 = XuCTSn1 00 = Input 10 = EXTDMA_ACK1 00 = Input 10 = EXTDMA_ACK0 00 = Input 10 = EXTDMA_REQ1 00 = Input 10 = EXTDMA_REQ0 00 = Input 10 = PWM_TOUT3 00 = Input 10 = PWM_TOUT2 00 = Input 10 = PWM_TOUT1 00 = Input 10 = PWM_TOUT0 00 = Input 10 = PWM_ECLK Description 01 = Output 11 = IrDA_RXD 01 = Output 11 = IrDA_TXD 01 = Output 11 = IrDA_SDBW 01 = Output 11 = RTC_ALMINT 01 = Output 11 = XkpCOL4 01 = Output 11 = XkpCOL3 01 = Output 11 = XkpCOL2 01 = Output 11 = XkpCOL1 01 = Output 11 = XkpCOL0 01 = Output 11 = XkpROW4 01 = Output 11 = XkpROW3 01 = Output 11 = XkpROW2 01 = Output 11 = XkpROW1 20-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR GPIO MIDDLE PORT CONTROL REGISTER (GPCON_M) If GP11 - GP18 will be used for wakeup signals at power down mode, the ports will be set in Interrupt mode. Register GPCON_M Address 0x44800004 R/W R/W Description Configures the pins of middle ports[18:11] Reset Value 0x0 GPCON_M GP18 GP17 GP16 GP15 GP14 GP13 GP12 GP11 Bit [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = EINT18 00 = Input 10 = EINT17 00 = Input 10 = EINT16 00 = Input 10 = EINT15 00 = Input 10 = EINT14 00 = Input 10 = EINT13 00 = Input 10 = EINT12 00 = Input 10 = EINT11 Description 01 = Output 11 = XkpROW0 01 = Output 11 = XspiCLK 01 = Output 11 = XspiMISO 01 = Output 11 = XspiMOSI 01 = Output 11 = RTC_ALMINT 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 20-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS GPIO LOWER PORT CONTROL REGISTER (GPCON_L) If GP8 - GP10 will be used for wakeup signals at power down mode, the ports will be set in Interrupt mode. Register GPCON_L Address 0x44800008 R/W R/W Description Configures the pins of lower ports[10:0] Reset Value 0x0 GPCON_L GP10 GP9 GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 Bit [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = Reserved 00 = Input 10 = EINT9 00 = Input 10 = EINT8 00 = Input 10 = EINT7 00 = Input 10 = EINT6 00 = Input 10 = EINT5 00 = Input 10 = EINT4 00 = Input 10 = EINT3 00 = Input 10 = EINT2 00 = Input 10 = EINT1 00 = Input 10 = EINT0 Description 01 = Output 11 = Reserved 01 = Output 11 = EXTDMA_ACK1 01 = Output 11 = EXTDMA_ACK0 01 = Output 11 = EXTDMA_REQ1 01 = Output 11 = EXTDMA_REQ0 01 = Output 11 = PWM_TOUT3 01 = Output 11 = PWM_TOUT2 01 = Output 11 = PWM_TOUT1 01 = Output 11 = PWM_TOUT0 01 = Output 11 = PWM_ECLK 01 = Output 11 = Reserved 20-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR GPIO PORT DATA REGISTER (GPDAT) Register GPDAT Address 0x4480000C R/W R/W Description The data register for all ports[31:0] Reset Value Undefined GPDAT GP[31:0] Bit [31:0] Description When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as function pin, undefined value will be read. GPIO PORT PULL UP RESISTER CONTROL REGISTER (GPPU) Register GPPU Reserved Address 0x44800010 0x44800014 R/W R/W Reserved Description Pull-up disable register for all ports[31:0] Reset Value 0x0 Undefined GPPU GP[31:0] Bit [31:0] Description 0 : The pull up function attached to to the corresponding port pin is enabled. 1 : The pull up function is disabled. 20-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS EXTERNAL INTERRUPT CONTROL REGISTER (EXTINTC0) The 18 external interrupts can be requested by various signaling methods. The EXTINTC register configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. To recognize the level interrupt, the valid logic level on EXTINTCn pin must be retained for 40ns at least because of the noise filter. (EINT[9:0]) Register EXTINTC0 Address 0x44800018 R/W R/W Description External Interrupt control Register 0 Reset Value 0x0 EXTINTC0 Reserved EXTINT2 Bit [11] [10:8] Description This bit is reserved and the value should be `0' Setting the signaling method of the EINT2. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered This bit is reserved and the value should be `0' Setting the signaling method of the EINT1. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered This bit is reserved and the value should be `0' Setting the signaling method of the EINT0. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved EXTINT1 [7] [6:4] Reserved EXTINT0 [3] [2:0] 20-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR EXTERNAL INTERRUPT CONTROL REGISTER (EXTINTC1) Register EXTINTC1 Address 0x4480001C R/W R/W Description External Interrupt control Register 1 Reset Value 0x0 EXTINTC1 Reserved EXTINT9 Bit [31:27] [26:24] Description This bit is reserved and the value should be `0' Setting the signaling method of the EINT9. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered This bit is reserved and the value should be `0' Setting the signaling method of the EINT8. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered This bit is reserved and the value should be `0' Setting the signaling method of the EINT7. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered This bit is reserved and the value should be `0' Setting the signaling method of the EINT6. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered This bit is reserved and the value should be `0' Setting the signaling method of the EINT5. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered This bit is reserved and the value should be `0' Setting the signaling method of the EINT4. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered This bit is reserved and the value should be `0' Setting the signaling method of the EINT3. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved EXTINT8 [23] [22:20] Reserved EXTINT7 [19] [18:16] Reserved EXTINT6 [15] [14:12] Reserved EXTINT5 [11] [10:8] Reserved EXTINT4 [7] [6:4] Reserved EXTINT3 [3] [2:0] 20-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS EXTERNAL INTERRUPT CONTROL REGISTER (EXTINTC2) Register EXTINTC2 Address 0x44800020 R/W R/W Description External Interrupt control Register 2 Reset Value 0x0 EXTINTC2 FLTEN18 EXTINT18 Bit [31] [30:28] Filter Enable for EINT18 Description 0 = Disable 1= Enable Setting the signaling method of the EINT18. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT17 0 = Disable 1= Enable Setting the signaling method of the EINT17. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT16 0 = Disable 1= Enable Setting the signaling method of the EINT16. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT15 0 = Disable 1= Enable Setting the signaling method of the EINT15. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT14 0 = Disable 1= Enable Setting the signaling method of the EINT14. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT13 0 = Disable 1= Enable Setting the signaling method of the EINT13. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT12 0 = Disable 1= Enable Setting the signaling method of the EXTINT12. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT11 0 = Disable 1= Enable Setting the signaling method of the EINT11. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered FLTEN17 EXTINT17 [27] [26:24] FLTEN16 EXTINT16 [23] [22:20] FLTEN15 EXTINT15 [19] [18:16] FLTEN14 EXTINT14 [15] [14:12] FLTEN13 EXTINT13 [11] [10:8] FLTEN12 EXTINT12 [7] [6:4] FLTEN11 EXTINT11 [3] [2:0] 20-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR EXTERNAL INTERRUPT FILTER CONTROL REGISTER (EINTFLTn) EINTFLTn control the length of filter for 8 external interrupts (EINT[18:11]). Register EINTFLT0 EINTFLT1 Address 0x44800024 0x44800028 R/W R/W R/W Description External Interrupt Control Register External Interrupt Control Register Reset Value 0x0 0x0 EINTFLT0 FLTCLK14 EINTFLT14 FLTCLK13 EINTFLT13 FLTCLK12 EINTFLT12 FLTCLK11 EINTFLT11 Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter clock of EINT14 0 = PCLK 1= XsEXTCLK/XsXTIN/RTC_CLKNOTE Filtering width of EINT14 Filter clock of EINT13 0 = PCLK 1= XsEXTCLK/XsXTIN/RTC_CLKNOTE Filtering width of EINT13 Filter clock of EINT12 0 = PCLK 1= XsEXTCLK/XsXTIN/RTC_CLKNOTE Filtering width of EINT12 Filter clock of EINT11 NOTE 0 = PCLK 1= XsEXTCLK/XsXTIN/RTC_CLK Filtering width of EINT11 EINTFLT1 FLTCLK18 EINTFLT18 FLTCLK17 EINTFLT17 FLTCLK16 EINTFLT16 FLTCLK15 Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] Description Filter clock of EINT18 0 = PCLK 1= XsEXTCLK/XsXTIN/RTC_CLKNOTE Filtering width of EINT18 Filter clock of EINT17 0 = PCLK 1= XsEXTCLK/XsXTIN/RTC_CLKNOTE Filtering width of EINT17 Filter clock of EINT16 NOTE 0 = PCLK 1= XsEXTCLK/XsXTIN/RTC_CLK Filtering width of EINT16 Filter clock of EINT15 NOTE 0 = PCLK 1= XsEXTCLK/XsXTIN/RTC_CLK EINTFLT15 [6:0] Filtering width of EINT15 NOTE: When the filter clock bit is `1', the source clock for filter is determined by the value of XgREFCLKSEL[0] pin and the value of ALIVECON[0]. 20-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS EXTERNAL INTERRUPT MASK REGISTER (EINTMASK)) Interrupt mask register for 18 external interrupts (EINT[18:11, 9:0]). Register EINTMASK Address 0x44800034 R/W R/W Description External interupt mask Register Reset Value 0x0007FFFF EINTMASK EINT18 EINT17 EINT16 EINT15 EINT14 EINT13 EINT12 EINT11 Reserved EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 Bit [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt Reserved 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt Description 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 20-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR EXTERNAL INTERRUPT PENDING REGISTER (EINTPEND) Interrupt pending register for 18 external interrupts (EINT[18:11, 9:0]). If the S3C24A0 wake-up from sleep mode by RTC alarm, the PMWKUP bit is set instead of INT_RTC bit in INTPND and INTSRCPND register. You can clear a specific bit of EINTPEND register by writing a data (`1') to this register. It clears only the bit positions of EINTPEND corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are with no change. Register EINTPEND Address 0x44800038 R/W R/W Description External Interupt Pending Register Reset Value 0x0 EINTPEND PMWKUP EINT18 EINT17 EINT16 EINT15 EINT14 EINT13 EINT12 EINT11 Reserved EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 Bit [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] RTC Alarm Interrupt. 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur Reserved 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur 0 = Not occur Description 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 1= Occur interrupt 20-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS PERIPHERAL PORT PULL UP CONTROL REGISTER (PERIPU) Pull up control register for peripheral port in normal mode. Register PERIPU Address 0x44800040 R/W R/W Description Controlled Pull-up Register Reset Value 0x00004000 PERIPU Reserved PERIPU26 Reserved PERIPU24 Reserved PERIPU14 PERIPU13 PERIPU12 PERIPU11 PERIPU10 PERIPU9 PERIPU8 Reserved PERIPU4 PERIPU3 PERIPU2 Reserved Bit [31:27] [26] [25] [24] [23:15] [14] [13] [12] [11] [10] [9] [8] [7:5] [4] [3] [2] [1:0] Reserved Pull-up for XmsSDIO port 0 : Enabled Reserved Pull-up for XsdDAT[3:0] ports 0 : Enabled Reserved Description 1 : Disabled 1 : Disabled Pull-up for XrADDR[25:18] ports 0 : Enabled 0 : Enabled 0 : Enabled 0 : Enabled 0 : Enabled 0 : Enabled 0 : Enabled Reserved Pull-up for XrDATA[15:0] ports 0 : Enabled Reserved Pull-up for XpDATA[31:0] ports 0 : Enabled Reserved 1 : Disabled 1 : Disabled 1 : Disabled 1 : Disabled 1 : Disabled 1 : Disabled 1 : Disabled 1 : Disabled 1 : Disabled Pull-up for XciCDATA[7:0] ports Pull-up for XmiADR[10:0] ports Pull-up for XmiDATA[7:0] ports Pull-up for XspiCLK and XspiMOSI ports Pull-up for X2sLRCK and X2sCLK ports Pull-up for XspiMISO port 20-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR ALIVE CONTROL REGISTER (ALIVECON) ALIVECON register reports reset status and battery fault status. The clock for alive-block in sleep mode can be selected. Register ALIVECON Address 0x44800044 R/W R/W Description Alive Control Register Reset Value 0x0 ALIVECON BATFLT SOFTRST WDTRST WARMRST Reserved SLEEPRST Bit [7] [6] [5] [4] [3:2] [1] Description 0 - Battery fault has not been asserted 1 - Battery fault has been asserted 0 - SW reset has not been asserted 1 - SW reset has been asserted 0 - Watch-Dog-Timer reset has not been asserted 1 - Watch-Dog-Timer reset has been asserted 0 - Warm reset has not been asserted 1 - Warm reset has been asserted Reserved This bit does not set automatically. Users must set this bit before enter sleep mode. 0 - Sleep mode wake-up operation has not been asserted 1 - Sleep mode wake-up operation has been asserted AliveCLKsel [0] XsXTIN and XsEXTCLK is selected by XgREFCLKSEL[0] pin when the XgREFCLKSEL[0] is high, the EXT_CLK is selected. 0 : XsXTIN / XsEXTCLK 1 : RTC_CLK NOTE: The asserted value, which is set automatically by hardware, should be cleared by software after checking the status. 20-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS GPIO OUTPUT DATA REGISTER (GPDAT_SLEEP) GPIO port output data register in sleep mode. In sleep mode the value of GPDAT is meaningless. Register GPDAT_SLEEP Address 0x44800048 R/W R/W Description Output Data for Sleep Mode Reset Value 0x0 GPDAT_SLEEP GPDAT_SLEEP[31:0] Bit Description [31:0] these value are propagated to corresponding ports/pins, if GPOEN_SLEEP is activated at sleep mode. GPIO OUTPUT CONTROL REGISTER FOR SLEEP MODE (GPOEN_SLEEP) GPOEN_SLEEP register controls GPIO port with output or Hi-z state. Register GPOEN_SLEEP Address 0x4480004C R/W R/W Description GPIO output enable control for sleep mode Reset Value 0xFFFF_FFFF GPOEN_SLEEP GPOEN_SLEEP[31:0] Bit [31:0] Description 0 : Make GPIO output port in sleep mode. 1 : Make GPIO Hi-z state in sleep mode. GPIO PULL UP CONTROL REGISTER FOR SLEEP MODE (GPPU_SLEEP) Pull up control register for GPIO port in sleep mode. Register GPPU_SLEEP Address 0x44800050 R/W R/W Description GPIO Pull-up Control Register for sleep mode Reset Value 0xFFFF_FFFF GPPU_SLEEP GPPU_SLEEP[31:0] Bit [31:0] Description 0 : The pull up function attached to to the corresponding port pin is enabled in sleep mode. 1 : The pull up function is disabled in sleep mode. 20-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR PERIPHERAL PORT OUTPUT DATA REGISTER FOR SLEEP MODE (PERIDAT_SLEEP0) Peripheral port output data register in sleep mode. These data is meaningful only when the PERIOEN_SLEEP is enabled. Register PERIDAT_SLEEP0 Address 0x44800054 R/W R/W Description Output data register for sleep mode Reset Value 0x8095_A220 PERIDAT_SLEEP0 PERIDAT031 PERIDAT030 PERIDAT029 Reserved PERIDAT027 PERIDAT026 PERIDAT025 PERIDAT024 PERIDAT023 PERIDAT022 PERIDAT021 PERIDAT020 PERIDAT019 PERIDAT018 PERIDAT017 PERIDAT016 PERIDAT015 PERIDAT014 PERIDAT013 PERIDAT012 Reserved PERIDAT07 PERIDAT06 PERIDAT05 PERIDAT04 PERIDAT03 PERIDAT02 PERIDAT01 PERIDAT00 Bit [31] [30] [29] [28] [27] [26] [25 [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11:8] [7] [6] [5] [4] [3] [2] [1] [0] Description XsRSTOUTn port output data XmsSDIO and XsdDAT[3:0] ports output data XmsSCLKO and XmsBS ports output data Reserved XvVD[17:0] ports output data XvVSYNC, XvHSYNC and XvVCLK ports output data XciRSTn port output data XciCLK port output data XmiIRQn port output data XmiDATA[7:0] and XgMONHCLK ports output data XudDN port output data XudDP port output data XusDN[1:0] ports output data XusDP[1:0] ports output data X97SYNC and X97SDO ports output data X97RESETn port output data XspiCLK and XspiMOSI ports output data X2sCDCLK and X2sDO ports output data X2sLRCK and X2sCLK ports output data XuTXD0 and XuRTS0 ports output data Reserved XpDATA[31:0] ports output data XpDQM[3:0] and XpADDR[14:0] ports output data XpCSN[1:0], XpCASn and XpRASn ports output data XpCKE and XpSCLK ports output data XrDATA[15:0] ports output data XrADDR[25:18] ports output data XrCSn[2:0], XrWEn, XrOEn and XrnWBE[1:0] ports output data XfCLE and XfALE ports output data Reset Value 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 2 0 0 1 0 0 0 0 0 20-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS PERIPHERAL PORT OUTPUT DATA REGISTER FOR SLEEP MODE (PERIDAT_SLEEP1) Peripheral port output data register in sleep mode. These data is meaningful only when the PERIOEN_SLEEP is enabled. Register PERIDAT_SLEEP1 Address 0x44800058 R/W R/W Description Output data register for sleep mode Reset Value 0x8095_A220 PERIDAT_SLEEP1 Reserved PERIDAT16 PERIDAT15 PERIDAT14 Reserved PERIDAT12 PERIDAT11 PERIDAT10 Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Reserved XpWEn port output data XjRTCK port output data Description Reset Value 0 1 1 1 1 0 1 0 X2cSCL, X2cSDA ports output data Reserved XrADDR[17:0] ports output data XspiMISO port output data XjTDO port output data 20-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR PERIPHERAL PORT OUTPUT CONTROL REGISTER FOR SLEEP MODE (PERIOEN_SLEEP0) Peripheral port output control register for each port in sleep mode. PERIOEN_SLEEP[8, 6] bits are used for suspend enabler also in stop mode. Register PERIOEN_SLEEP0 Address 0x4480005C R/W R/W Description Output control register0 for sleep mode Reset Value 0x003F_03E3 PERIOEN_SLEEP0 Reserved PERIOEN021 Reserved PERIOEN015 PERIOEN014 PERIOEN013 PERIOEN012 Reserved PERIOEN010 Reserved PERIOEN08 Reserved PERIOEN06 PERIOEN05 PERIOEN04 PERIOEN03 Reserved PERIOEN01 PERIOEN00 Bit [31:22] Reserved [21] Description Select XmiDATA[7:0] pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XjTDO pin output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XsXTOUT pin output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XsdDAT[3:0] pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XmsSDIO pin output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Reserved Select XvVD[17:0] pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Reserved Select XudDP and XudDN pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Reserved Select XusDP[1:0] and XusDN[1:0] pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XspiCLK and XspiMOSI pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select X2sLRCK and X2sCLK pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XspiMISO pin output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Reserved Select XpDATA[31:0] pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XrDATA[15:0] pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Reset Value 0 1 0x1f 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 [20:16] Reserved [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 20-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS PERIPHERAL PORT OUTPUT CONTROL REGISTER FOR SLEEP MODE (PERIOEN_SLEEP1) Register PERIOEN_SLEEP1 Address 0x44800060 R/W R/W Description Output control register1 for sleep mode Reset Value 0x0037_D802 PERIOEN_SLEEP1 Reserved PERIOEN119 PERIOEN118 PERIOEN117 PERIOEN116 PERIOEN115 PERIOEN114 PERIOEN113 PERIOEN112 PERIOEN111 PERIOEN110 PERIOEN19 Reserved PERIOEN15 PERIOEN14 Bit [31:20] Reserved [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8:6] [5] [4] Description Select XsRSTOUTn pin output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XmsBS and XmsSCLKO pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XvDEN pin output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XvVSYNC, XvHSYNC and XvVCLK pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XciRSTn pin output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XciCLK pin output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XmiIRQn and XgMONHCLK pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select X97SYNC and X97SDO pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select X97RESETn pin output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select X2sCDCLK and X2sDO pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XuTXD0 and XuRTSn0 pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Reserved Select XpDQM[3:0] and XpADDR[14:0] pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XpWEn, XpCSn[1:0], XpCASn and XpRASn pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XpCKE and XpSCLK pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XrADDR[17:0] pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XrCSn[2:0], XrWEn, XrOEn and XrnWBE[1:0] pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Select XfCLE and XfALE pins output or Hi-z 0: Enable(Output) 1: Disable(Hi-z) Reset Value 0x3 0 1 1 1 1 1 0 1 1 0 0 0 0 0 PERIOEN13 PERIOEN12 PERIOEN11 [3] [2] [1] 0 0 1 PERIOEN10 [0] 0 20-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR PERIPHERAL PORT PULL UP CONTROL REGISTER FOR SLEEP MODE (PERIPU_SLEEP) Control pull up resister attached to the corresponding peripheral port pin in sleep mode. Register PERIPU_SLEEP Address 0x44800064 R/W R/W Description Controlled Pull-up Register for slee mode Reset Value 0x0 PERIPU_SLEEP Reserved PERIPU26 Reserved PERIPU24 Reserved PERIPU11 PERIPU10 PERIPU9 PERIPU8 Reserved PERIPU4 Reserved PERIPU2 Reserved Bit [32:27] Reserved [26] [25] [24] Description Control internal pull-up resister for XmsSDIO in sleep mode 0 : Enabled 1 : Disabled Reserved Control internal pull-up resister for XsdDAT[3:0] in sleep mode 0 : Enabled 1 : Disabled Control internal pull-up resister for XmiDATA[7:0] in sleep mode 0 : Enabled 1 : Disabled Control internal pull-up resister for XspiCLK and XspiMOSI in sleep mode 0 : Enabled 1 : Disabled Control internal pull-up resister for X2sLRCK and X2sCLK in sleep mode 0 : Enabled 1 : Disabled Control internal pull-up resister for XspiMISO in sleep mode 0 : Enabled 1 : Disabled Reserved in sleep mode Control internal pull-up resister for XrDATA[15:0] in sleep mode 0 : Enabled 1 : Disabled Reserved Control internal pull-up resister for XpDATA[31:0] in sleep mode 0 : Enabled 1 : Disabled Reserved [23:12] Reserved [11] [10] [9] [8] [7:5] [4] [3] [2] [1:0] 20-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS RESET COUNT COMPARE REGISTER (RSTCNT) Compared counter value for the Power Settle-down-time wait. Register RSTCNT Address 0x44800068 R/W R/W Description Reset Count Compare Register Reset Value 0x0 RSTCNT RstCnt[7:0] Bit [7:0] Description After wake-up from the SLEEP mode, the S3C24A0 power-management logic adds an external power-source settle-down-wait time by holding the internal reset signal to low (forces the internal reset is active). The AliveCLK is the reference clock source for the power-management circuitry. It can be selected from the external clock sources or the RTC clock. Reset duration = (RstCnt[7] x 16384 RstCnt[6] X 3 X 2048 RstCnt[5] X 7 X 256 RstCnt[4] X 7 X 32 RstCnt[3] X 3 X 8 RstCnt[2:0] ) x 32 x 1/AliveCLK 20-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 I/O PORTS S3C24A0 RISC MICROPROCESSOR GENERAL PURPOSE RAM ARRAY (GPRAMn) General purpose RAM array, 16x32-bit. These memory array connected alive-block, so their contents be maintained in sleep mode. Register GPRAM0 GPRAM1 GPRAM2 GPRAM3 GPRAM4 GPRAM5 GPRAM6 GPRAM7 GPRAM8 GPRAM9 GPRAM10 GPRAM11 GPRAM12 GPRAM13 GPRAM14 GPRAM15 Address 0x44800080 0x44800084 0x44800088 0x4480008C 0x44800090 0x44800094 0x44800098 0x4480009C 0x448000A0 0x448000A4 0x448000A8 0x448000AC 0x448000B0 0x448000B4 0x448000B8 0x448000BC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description General purpose RAM word 0 General purpose RAM word 1 General purpose RAM word 2 General purpose RAM word 3 General purpose RAM word 4 General purpose RAM word 5 General purpose RAM word 6 General purpose RAM word 7 General purpose RAM word 8 General purpose RAM word 9 General purpose RAM word 10 General purpose RAM word 11 General purpose RAM word 12 General purpose RAM word 13 General purpose RAM word 14 General purpose RAM word 15 Reset Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 20-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O PORTS NOTES 20-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE CAMERA INTERFACE (PRELIMINARY) OVERVIEW This specification defines the interface of camera. The camera interface of S3C24A0 consists of seven parts. They are the pattern mux, capturing unit, preview scaler, codec scaler, preview DMA, codec DMA, and SFR. The camera interface supports ITU R BT-601/656 YCbCr 8/16-bit standard. Maximum input size is 4096x4096 pixels (2048x2048 pixels for scaling). There are two scalers. The one is the preview scaler, which is dedicated to generate small size image as PIP(Picture In Picture). The other one is the codec scaler, which is dedicated to generate codec useful image like plane type YCbCr 4:2:0 or 4:2:2. Two master DMAs can do mirroring and rotating the captured image for mobile environments. These features are very useful at folder type cellular phone. And test pattern generation can be used to calibration of input sync signals as HREF,VSYNC. Also, video sync signals and pixel clock polarity can be inverted in the camera interface side with using register setting. T_patternMux ITU-R BT 601/656 CatchCam CamIf SFR YCbCr 4:2:2 Preview Scaler & RGB Formatter Preview DMA AHB bus Figure 21-1. Camera interface overview YCbCr 4:2:X Codec Scaler Codec DMA 21-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE Features - ITU-R BT 601/656 8/16-bit mode - DZI (Digital Zoom In) capability - Programmable polarity of video sync signals - Up to 4096 x 4096 pixel input (Up to 2048 x 2048 pixel input for scaling) - Image mirror and rotation (X-axis mirror, Y-axis mirror, and 180rotation) - PIP and codec input image generation (RGB 16/24-bit format and YCbCr 4:2:0/4:2:2 format) EXTERNAL INTERFACE The camera interface of S3C24A0 can support the next video standards. - ITU-R BT 601 YCbCr 8/16-bit mode - ITU-R BT 656 YCbCr 8-bit mode SIGNAL DESCRIPTION Name XciPCLK XciVSYNC XciHREF XciYDATA [7:0] XciCDATA [7:0] XciCLK Note 1) I/O I I I I I 1) Active H/L H/L - Description Pixel Clock, driven by the camera processor Frame Sync, driven by the camera processor Horizontal Sync, driven by the camera processor Pixel Data for YcbCr in 8-bit mode or for Y in 16-bit mode, driven by the camera processor Pixel Data for CbCr in 16-bit mode, driven by the camera processor Master Clock to the Camera processor O XciRSTn O H/L Software Reset or Power Down for the Camera processor I/O direction is on the S3C24A0 side. I : input, O : output, B : bi-direction Table 21-1. Camera interface signal description 21-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM 1 frame XciVSYNC Vertical lines XciHREF XciHREF Horizontal width XciPCLK 8-bit mode XciYDATA[7:0] Y Cb Y Cr Y Cb 16-bit mode XciYDATA[7:0] XciCDATA[7:0] Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Figure 21-2. ITU-R BT 601 Input timing diagram XciPCLK XciYDATA[7:0] FF 00 00 XY Y Cb Cr FF 00 00 XY Video timing reference codes Pixel data Video timing reference codes Figure 21-3. ITU-R BT 656 Input timing diagram There are two timing reference signals in ITU-R BT 656 format, one is at the beginning of each video data block (start of active video, SAV) and the other is at the end of each video data block(end of active video, EAV) as shown in Figure 21-3 and Table 21-2. Data bit number 9 (MSB) 8 7 First word 1 1 1 Second word 0 0 0 Third word 0 0 0 Fourth word 1 F V 21-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE 6 5 4 3 2 1 (Note 1) 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H P3 P2 P1 P0 0 0 Note 1) For compatibility with existing 8-bit interfaces, the values of bits D1 and D0 are not defined. F = 0 (during field 1), 1 (during field 2) V = 0 (elsewhere), 1 (during field blanking) H = 0 (in SAV : Start of Active Video), 1 (in EAV : End of Active Video) P0, P1, P2, P3 = protection bit Table 21-2. Video timing reference codes of ITU-656 format Camera interface logic can catch the video sync bits like H(SAV,EAV) and V(Frame Sync) after reserved data as "FF-00-00". 21-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE EXTERNAL CONNECTION GUIDE All input signals of camera interface should not occur inter-skewing to pixel clock line. Recommend next pin location and routing. XciCLK XciRSTn Chip IO Camera I/F No Skew XciVSYNC Camera XciHREF No Skew XciPCLK XciYDATA[7:0] XciCDATA[7:0] No Skew Figure 21-4. IO connection guide 8-BIT MODE In this case, Camera data are fed into S3C24A0 through only XciYDATA[7:0]. Therefore, Signal levels of XciCDATA[7:0] are determined in appropriate value to prevent leakage current. If you connect these signals to ground, internal pull-up must be disabled at both normal and power saving mode. 16-BIT MODE In this case, Camera data are fed into S3C24A0 through XciYDATA[7:0] for Y and XciCDATA[7:0] for CbCr. 21-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE CAMERA INTERFACE OPERATION TWO DMA PORTS Camera interface has two DMA ports. P-port(Preview port) and C-port(Codec port) are separated from each other on AHB bus. At the view of system bus, two ports are independent. The P-port stores the RGB image data into memory for PIP. The C-port stores the YCbCr 4:2:0 or 4:2:2 image data into memory for Codec as MPEG-4, H.263, etc. These two master ports support the variable applications like DSC (Digital Steel Camera), MPEG-4 video conference, video recording, etc. For example, P-port image can be used as preview image, and C-port image can be used as JPEG image in DSC application. Also, the P-port or C-port can be disabled separately. Frame Memory (SDRAM) P-port External Camera Processor PIP RGB ITU format CAMIF C-port Codec image YCbCr 4:2:0 or YCbCr 4:2:2 Window cut Frame Memory (SDRAM) P-port External Camera Processor PIP RGB ITU format CAMIF C-port Codec image YCbCr 4:2:0 or YCbCr 4:2:2 Figure 21-7. Two DMA ports 21-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE CLOCK DOMAIN Camera interface has two clock domains. The one is the system bus clock, which is HCLK. The other is the pixel clock, which is XciPCLK. The system clock must be faster than pixel clock. As shown in figure 21-8, XciCLK must be divided from the fixed frequency like USB PLL clock. If external clock oscillator were used, XciCLK should be floated. The clock for internal scaler is system clock. It is not necessary that two clock domains are synchronized to each other. Other signals as XciPCLK should be connected similarly to schmitt-triggered level shifter. UPLL S3C24A0 fUSB Divide Counter USB PLL 96 MHz MPLL fmpll Variable Freq. fUSB /d XciCLK 1/1,1/2,1/ 3...~1/16 Divide Counter fmpll /d Normally use External Camera Processor Schmitt-triggered Level-shifter XciPCLK Camera Interface HCLK External MCLK Figure 21-8. Clock generation 21-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE FRAME MEMORY HIRERARCHY Frame memories consist of four ping-pong memories for each P- and C-ports. C-port ping-pong memories have three element memories that are luminance Y, chrominance Cb, and chrominance Cr. 4-pingpong Frame memory (SDRAM) P-port RGB 1 P-port RGB 2 P-port RGB 3 P-port RGB 4:4:4 ITU-601/656 YCbCr 4:2:2 8-bits AHB bus & Memorycontroller C-port Y 1 C-port Cb 1 C-port Cr 1 C-port Y 2 C-port Cb 2 C-port Cr 2 C-port Y 3 C-port Cb 3 C-port Cr 3 C-port Y 4 C-port Cb 4 C-port Cr 4 P-port RGB 4 Camera Interface C-port 4:2:0,2 Figure 21-9. Ping-pong memory hierarchy 21-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE MEMORY STORING METHOD The storing method to the frame memory is the little-endian method in codec path. The first entering pixels stored into LSB sides, and the last entering pixels stored into MSB sides. The carried data by AHB bus is 32-bit word. So, camera interface stores the each Y-Cb-Cr words by little endian style. For preview path, two different formats exist. One pixel (Color 1 pixel) is in one word for RGB 24-bit format. Otherwise, two pixels are in one word for RGB 16-bit format. Refer to Figure 21-10. Y4 Y3 Y2 Y1 Y8 Y7 Y6 Y5 Little endian method Y frame memory Cb4 ITU-601/656 YCbCr 4:2:2 8-bit input timing XciPCLK XciYDATA[7:0] Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Camera Interface Cb3 Cb2 Cb1 Cb8 Cb7 Cb6 Cb5 Little endian method Cb frame memory time Cr4 Cr3 Cr2 Cr1 Cr8 Cr7 Cr6 Cr5 Little endian method Cr frame memory 32-bit RGB RGB1 RGB2 RGB3 RGB4 RGB5 RGB6 RGB7 RGB8 RGB frame memory (24-bit) 32-bit 2 16-bit R5 G6 B5 1 RGB2/1 RGB4/3 RGB6/5 RGB8/7 RGB10/9 RGB12/11 RGB14/13 RGB16/15 RGB frame memory (16-bit) Figure 21-10. Memory storing style 21-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM FOR REGISTER SETTING The first register setting for frame capture command can be occurred in anywhere of frame period. But, it is recommend to do first setting at the VSYNC "L" state. VSYNC information can be read from status SFR. All command include ImgCptEn, is valid at VSYNC falling edge. Be sure that except first SFR setting, all command should be programmed in ISR(Interrupt Service Routine). It is not allowed for target size information to be changed during capturing operation. However, image mirror or rotation, windowing, and Zoom In settings are allowed to change in capturing operation. XciVSYNC XciHREF INTERRUPT Reserved Multi frame capturing Image Capture SFR setting (ImgCptEn) < Frame Capture Start > XciVSYNC XciHREF INTERRUPT In Capturing Image Capture Reserved New Command New SFR command < New command valid timing diagram > Figure 21-11. Timing diagram for register setting NOTE : FIFO overflow of codec port will be set if codec port is not operating when preview port is operated. If you want to use codec port under this case, you should stop preview port and reset CAMIF using SwRst bit of CIGCTRL register. Then clear overflow of codec port and set special function registers that you want. Overflow that doesn't affect normal operation will be set when camera module is turned on and 31th bit of CISRCFMT is `0'. We recommend that you set 31th bit of CISRCFMT to `1' before camera module is turned on if 21-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE you use ITU-R 601 format. If overflow is set before starting capturing, please clear overflow using clearing bits of CIWDOFST. TIMING DIAGRAM FOR LAST IRQ IRQ except LastIRQ is generated before image capturing. Last IRQ which means capture-end can be set by following timing diagram. LastIRQEn is auto-cleared and ,as mentioned, SFR setting in ISR is for next frame command. So, for adequate last IRQ, you should follow next sequence between LastIRQEn and ImgCptEn/ImgCptEn_CoSc/ImgCptEnPrSC. It is recommended that ImgCptEn/ImgCptEn_CoSc/ImgCptEnPrSC are set at same time and at last of SFR setting in ISR. FrameCnt which is read in ISR, means next frame count. On following diagram, last captured frame count is "1". That is, Frame 1 is the last-captured frame among frame 0~3. FrameCnt is increased by 1 at IRQ rising. ISR region ISR region ISR region ISR region VSYNC ImgCptEn LastIRQEn IRQ FrameCnt 3 0 1 2 Auto cleared Last IRQ 3 Capture O Capture O Capture O Capture X Figure 21-12. Timing diagram for last IRQ 21-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE SOFTWARE INTERFACE Camera Interface SFR (Special Function Register) CAMERA INTERFACE SPECIAL REGISTERS SOURCE FORMAT REGISTER Register CISRCFMT Address 0x48000000 R/W RW Description Input Source Format Reset Value 0 CISRCFMT ITU601_656n Bit [31] Description 1 : ITU-R BT.601 YCbCr 8/16-bit mode enable 0 : ITU-R BT.656 YCbCr 8-bit mode enable Cb,Cr value offset control. Initial State 0 UVOffset [30] 1 : +128 0 : +0 (normally used) 0 In16bit SourceHsize [29] [28:16] ITU-R BT 601 YCbCr 16-bit mode enable Source horizontal pixel number (must be 8's multiple) Input YCbCr order inform for input 8/16-bit mode 8-bit mode (In16bit = 0) 16-bit mode (In16bit = 1) 00 : Y Y Y Y 0 0 Order422 [15:14] 00 : YCbYCr 01 : YCrYCb 10 : CbYCrY 11 : CrYCbY CbCrCbCr 01 : Y Y Y Y CrCbCrCb Others : Forbidden 0 SourceVsize [12:0] Source vertical pixel number (must be 16's multiple for JPEG DCT.) 0 21-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE WINDOW OPTION REGISTER Register CIWDOFST Address 0x48000004 R/W RW Description Window offset register Reset Value 0 SourceHsize Original Input SourceVsize TargetHsize_xx TargetVsize_xx Window Cut : WinHorOfst : WinVerOfst TargetHsize_xx = TargetHsize_Co or TargetHsize_Pr Figure 21-13 Window offset scheme CIWDOFST WinOfsEn Bit [31] 1 : window offset enable 0 : no offset Description Initial State 0 ClrOvCoFiY [30] 1 : clear the overflow indication flag of input CODEC FIFO Y 0 : normal Window horizontal offset by pixel unit. (The size of offset must be multiple of 8) 1 : clear the overflow indication flag of input CODEC FIFO Cb 0 : normal 1 : clear the overflow indication flag of input CODEC FIFO Cr 0 : normal 1 : clear the overflow indication flag of input PREVIEW FIFO Cb 0 : normal 1 : clear the overflow indication flag of input PREVIEW FIFO Cr 0 : normal Window vertical offset by pixel unit 0 WinHorOfst [26:16] 0 ClrOvCoFiCb [15] 0 ClrOvCoFiCr [14] 0 ClrOvPrFiCb [13] 0 ClrOvPrFiCr WinVerOfst [12] [10:0] 0 0 Clear bits should be set by zero after clearing the flags. 21-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE GLOBAL CONTROL REGISTER Register CIGCTRL Address 0x48000008 R/W RW Description Global control register Reset Value 0x20000000 CIGCTRL SwRst CamRst Reserved Bit [31] [30] [29] Description Camera interface software reset External camera processor Reset or Power Down control Should be `1'. This register should be set at only ITU-T 601 8-bit mode. Not allowed with input 16-bit mode or ITU-T 656 mode. (max. 1280 X 1024) Initial State 0 0 1 TestPattern [28:27] 00 : external camera processor input (normal) 01 : color bar test pattern 10 : horizontal increment test pattern 11 . vertical increment test pattern 0 InvPolPCLK [26] 1 : inverse the polarity of XciPCLK 0 : normal(Camera data is fetched at rising edge of XciPCLK) 1 : inverse the polarity of XciVSYNC 0 : normal 1 : inverse the polarity of XciHREF 0 : normal 0 InvPolVSYNC [25] 0 InvPolHREF [24] 0 21-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE Y1 START ADDRESS REGISTER Register CICOYSA1 Address 0x48000018 R/W RW st Description 1 Y frame start address for codec DMA Reset Value 0 CICOYSA1 CICOYSA1 Bit [31:0] st Description 1 Y frame start address for codec DMA Initial State 0 Y2 START ADDRESS REGISTER Register CICOYSA2 Address 0x4800001c R/W RW 2 nd Description Y frame start address for codec DMA Reset Value 0 CICOYSA2 CICOYSA2 Bit [31:0] Description 2nd Y frame start address for codec DMA Initial State 0 Y3 START ADDRESS REGISTER Register CICOYSA3 Address 0x48000020 R/W RW rd Description 3 Y frame start address for codec DMA Reset Value 0 CICOYSA3 CICOYSA3 Bit [31:0] Description 3rd Y frame start address for codec DMA Initial State 0 Y4 START ADDRESS REGISTER Register CICOYSA4 Address 0x48000024 R/W RW th Description 4 Y frame start address for codec DMA Reset Value 0 CICOYSA4 CICOYSA4 Bit [31:0] Description 4th Y frame start address for codec DMA Initial State 0 CB1 START ADDRESS REGISTER Register CICOCBSA1 Address 0x48000028 R/W RW st Description 1 Cb frame start address for codec DMA Reset Value 0 21-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE CICOCBSA1 CICOCBSA1 Bit [31:0] st Description 1 Cb frame start address for codec DMA Initial State 0 CB2 START ADDRESS REGISTER Register CICOCBSA2 Address 0x4800002c R/W RW nd Description 2 Cb frame start address for codec DMA Reset Value 0 CICOCBSA2 CICOCBSA2 Bit [31:0] nd Description 2 Cb frame start address for codec DMA Initial State 0 CB3 START ADDRESS REGISTER Register CICOCBSA3 Address 0x48000030 R/W RW rd Description 3 Cb frame start address for codec DMA Reset Value 0 CICOCBSA3 CICOCBSA3 Bit [31:0] Description 3rd Cb frame start address for codec DMA Initial State 0 CB4 START ADDRESS REGISTER Register CICOCBSA4 Address 0x48000034 R/W RW th Description 4 Cb frame start address for codec DMA Reset Value 0 CICOCBSA4 CICOCBSA4 Bit [31:0] Description 4th Cb frame start address for codec DMA Initial State 0 CR1 START ADDRESS REGISTER Register CICOCRSA1 Address 0x48000038 R/W RW st Description 1 Cr frame start address for codec DMA Reset Value 0 CICOCRSA1 CICOCRSA1 Bit [31:0] Description 1st Cr frame start address for codec DMA Initial State 0 21-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE CR2 START ADDRESS REGISTER Register CICOCRSA2 Address 0x4800003c R/W RW 2 nd Description Cr frame start address for codec DMA Reset Value 0 CICOCRSA2 CICOCRSA2 Bit [31:0] nd Description 2 Cr frame start address for codec DMA Initial State 0 CR3 START ADDRESS REGISTER Register CICOCRSA3 Address 0x48000040 R/W RW rd Description 3 Cr frame start address for codec DMA Reset Value 0 CICOCRSA3 CICOCRSA3 Bit [31:0] Description 3rd Cr frame start address for codec DMA Initial State 0 CR4 START ADDRESS REGISTER Register CICOCRSA4 Address 0x48000044 R/W RW th Description 4 Cr frame start address for codec DMA Reset Value 0 CICOCRSA4 CICOCRSA4 Bit [31:0] Description 4th Cr frame start address for codec DMA Initial State 0 CODEC TARGET FORMAT REGISTER Register CICOTRGFMT Address 0x48000048 R/W RW Description Target image format of codec DMA Reset Value 0 21-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE X-axis flip Original image Y-axis flip 180' rotation Figure 21-14 Image mirror and rotation CICOTRGFMT Bit Description 1 : YCbCr 4:2:2 codec scaler input image format. Initial State In422_Co [31] 0 : YCbCr 4:2:0 codec scaler input image format. In this case, horizontal line decimation is performed before codec scaler. (normal) 1 : YCbCr 4:2:2 codec scaler output image format. This mode is mainly for S/W JPEG. 0 : YCbCr 4:2:0 codec scaler output image format. This mode is mainly for MPEG-4 codec and H/W JPEG DCT.(normal) Horizontal pixel number of target image for codec DMA (16's multiple) Image mirror and rotation for codec DMA 00 : Normal 0 Out422_Co [30] 0 TargetHsize_Co [28:16] 0 FlipMd_Co [15:14] 01 : X-axis mirror 10 : Y-axis mirror 11 : 180rotation 0 TargetVsize_Co [12:0] Vertical pixel number of target image for codec DMA (must be 16's multiple for JPEG DCT.) 0 21-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE CODEC DMA CONTROL REGISTER Register CICOCTRL Address 0x4800004c R/W RW Description Codec DMA control Reset Value 0 CICOCTRL Yburst1_Co Yburst2_Co Cburst1_Co Cburst2_Co Bit [23:19] [18:14] [13:9] [8:4] Description Main burst length for codec Y frames Remained burst length for codec Y frames Main burst length for codec Cb/Cr frames Remained burst length for codec Cb/Cr frames 1 : enable last IRQ at the end of frame capture (It is recommended Initial State 0 0 0 0 LastIRQEn_Co [2] to check the done signal of capturing image for JPEG.) 0 : normal 0 All burst lengthes should be one of the 2,4,8,16. Example 1. Target image size : QCIF (horizontal Y width = 176) 176 / 4 = 44 word. 44 % 8 = 4 main burst = 8, remained burst = 4 Example 2. Target image size : VGA (horizontal Y width = 640) 640 / 4 = 160 word. 160 % 16 = 0 main burst = 16, remained burst = 16 Example 3. Target image size : QCIF (horizontal C width = 88) 88 / 4 = 22 word. 22 % 4 = 2 main burst = 4, remained burst = 2 (HTRANS==INCR) REGISTER SETTING GUIDE FOR CODEC SCALER AND PREVIEW SCALER SRC_Width and DST_Width satisfy the following constraints. In SRC_Width case, the number of horizontal pixel can be represented to the power of 8. In DST_Width case, the number of horizontal pixel can be represented kn where n = 1,2,3, ... and k = 2/4/16 for 24bpp RGB/16bpp RGB/YCbCr image, respectively. TargetHsize should not be larger than SourceHsize. Similarly, TargetVsize should not be larger than SourceVsize. 21-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE SourceHsize Original Input SourceVsize TargetHsize_xx Scale Down TargetVsize_xx SRC_Width = SourceHsize SRC_Height = SourceVsize TargetHsize_xx = TargetHsize_Co or TargetHsize_Pr DST_Width = TargetHsize_xx DST_Height = TargetVsize_xx SourceHsize Original Input SourceVsize TargetHsize_xx Zoom In TargetVsize_xx : WinHorOfst : WinVerOfst SRC_Width = SourceHsize - (2 x WinHorOfst) SRC_Height = SourceVsize - (2 x WinVerOfst) TargetHsize_xx = TargetHsize_Co or TargetHsize_Pr DST_Width = TargetHsize_xx DST_Height = TargetVsize_xx Figure 21-15 Scaling scheme The other control registers of pre-scaled image size, pre-scale ratio, pre-scale shift ratio and main scale ratio are defined according to the following equations. If ( SRC_Width >= 64 x DST_Width ) { Exit(-1); /* Out Of Horizontal Scale Range */ } else if (SRC_Width >= 32 x DST_Width) { PreHorRatio_xx = 32; H_Shift = 5; } else if (SRC_Width >= 16 x DST_Width) { PreHorRatio_xx = 16; H_Shift = 4; } else if (SRC_Width >= 8 x DST_Width) { PreHorRatio_xx = 8; H_Shift = 3; } else if (SRC_Width >= 4 x DST_Width) { PreHorRatio_xx = 4; H_Shift = 2; } else if (SRC_Width >= 2 x DST_Width) { PreHorRatio_xx = 2; H_Shift = 1; } else { PreHorRatio_xx = 1; H_Shift = 0; } PreDstWidth_xx = SRC_Width / PreHorRatio_xx; MainHorRatio_xx = ( SRC_Width << 8 ) / ( DST_Width << H_Shift); If ( SRC_Height >= 64 x DST_Height ) { Exit(-1); /* Out Of Vertical Scale Range */ } else if (SRC_Height >= 32 x DST_Height) { PreVerRatio_xx = 32; V_Shift = 5; } else if (SRC_Height >= 16 x DST_Height) { PreVerRatio_xx = 16; V_Shift = 4; } 21-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE else if (SRC_Height >= 8 x DST_Height) { PreVerRatio_xx = 8; V_Shift = 3; } else if (SRC_Height >= 4 x DST_Height) { PreVerRatio_xx = 4; V_Shift = 2; } else if (SRC_Height >= 2 x DST_Height) { PreVerRatio_xx = 2; V_Shift = 1; } else { PreVerRatio_xx = 1; V_Shift = 0; } PreDstHeight_xx = SRC_Height / PreVerRatio_xx; MainVerRatio_xx = ( SRC_Height << 8 ) / ( DST_Height << V_Shift); SHfactor_xx = 10 - ( H_Shit + V_Shift); Note: In preview path, Pre-scaled H_width must be the less than 640. (The maximum size of preview path horizontal line buffer is 640.) 21-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE CODEC PRE-SCALER CONTROL REGISTER 1 Register CICOSCPRERATIO Address 0x48000050 R/W RW Description Codec pre-scaler ratio control Reset Value 0 CICOSCPRERATIO SHfactor_Co PreHorRatio_Co PreVerRatio_Co Bit [31:28] [22:16] [6:0] Description Shift factor for codec pre-scaler Horizontal ratio of codec pre-scaler Vertical ratio of codec pre-scaler Initial State 0 0 0 CODEC PRE-SCALER CONTROL REGISTER 2 Register CICOSCPREDST Address 0x48000054 R/W RW Description Codec pre-scaler destination format Reset Value 0 CICOSCPREDST PreDstWidth_Co PreDstHeight_Co Bit [27:16] [11:0] Description Destination width for codec pre-scaler Destination height for codec pre-scaler Initial State 0 0 CODEC MAIN-SCALER CONTROL REGISTER Register CICOSCCTRL Address 0x48000058 R/W RW Description Codec main-scaler control Reset Value 0 CICOSCCTRL Bit Description Codec scaler bypass for upper 2048 x 2048 size (In this case, ImgCptEn_CoSC and ImgCptEn_PrSC should be 0, but ImgCptEn should be 1. It is not allowed to capturing preview image. This mode is intended to capture JPEG input image for DSC application) In this case, input pixel buffering depends on only input FIFOs, so system bus should be not busy in this mode. Scale up/down flag for codec scaler(In 1:1 scale ratio, this bit should be "1") 00 = down 11 = up Initial State ScalerBypass_Co [31] 0 ScaleUpDown_Co [30:29] 00 MainHorRatio_Co [24:16] Horizontal scale ratio for codec main-scaler 0 21-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE CoScalerStart MainVerRatio_Co [15] [8:0] Codec scaler start Vertical scale ratio for codec main-scaler 0 0 CODEC DMA TARGET AREA REGISTER Register CICOTAREA Address 0x4800005c R/W RW Description Codec pre-scaler destination format Reset Value 0 CICOTAREA CICOTAREA Bit [25:0] Description Target area for codec DMA = Target H size x Target V size Initial State 0 CODEC STATUS REGISTER Register CICOSTATUS Address 0x48000064 R/W R Description Codec path status Reset Value 0 CICOSTATUS OvFiY_Co OvFiCb_Co OvFiCr_Co VSYNC Bit [31] [30] [29] [28] Description Overflow state of codec FIFO Y Overflow state of codec FIFO Cb Overflow state of codec FIFO Cr Camera VSYNC (This bit can be referred by CPU for first SFR setting after external camera muxing. And, it can be seen in the ITU-R BT 656 mode) 1:blank, 0: field Frame count of codec DMA (This counter value means the next frame number) Window offset enable status Flip mode of codec DMA Image capture enable of camera interface Image capture enable of codec path Status of signal level of XciVSYNC Initial State 0 0 0 0 FrameCnt_Co WinOfstEn_Co FlipMd_Co ImgCptEn_CamIf ImgCptEn_CoSC VSYNC_E [27:26] [25] [24:23] [22] [21] [20] 0 0 0 0 0 x 21-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE RGB1 START ADDRESS REGISTER Register CIPRCLRSA 1 Address 0x4800006c R/W st Description 1 RGB frame start address for preview DMA Reset Value 0 RW CIPRCLRSA1 CIPRCLRSA1 Bit [31:0] st Description 1 RGB frame start address for preview DMA Initial State 0 RGB2 START ADDRESS REGISTER Register CIPRCLRSA 2 Address 0x48000070 R/W RW Description 2nd RGB frame start address for preview DMA Reset Value 0 CIPRCLRSA2 CIPRCLRSA2 Bit [31:0] Description 2nd RGB frame start address for preview DMA Initial State 0 RGB3 START ADDRESS REGISTER Register CIPRCLRSA 3 Address 0x48000074 R/W RW Description 3rd RGB frame start address for preview DMA Reset Value 0 CIPRCLRSA3 CIPRCLRSA3 Bit [31:0] Description 3rd RGB frame start address for preview DMA Initial State 0 RGB4 START ADDRESS REGISTER Register CIPRCLRSA 4 Address 0x48000078 R/W RW Description 4th RGB frame start address for preview DMA Reset Value 0 CIPRCLRSA4 CIPRCLRSA4 Bit [31:0] Description 4th RGB frame start address for preview DMA Initial State 0 21-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW TARGET FORMAT REGISTER Register CIPRTRGFMT Address 0x4800007c R/W RW Description Target image format of preview DMA Reset Value 0 CIPRTRGFMT Bit Description Horizontal pixel number of target image for preview DMA . Initial State TargetHsize_Pr [28:16] 16bpp RGB : 4n(n=1,2,3, ...) 24bpp RGB : 2n(n=1,2,3, ...) Image mirror and rotation for preview DMA 00 : normal 0 FlipMd_Pr [15:14] 01 : x-axis mirror 10 : y-axis mirror 11 : 180 rotation 0 TargetVsize_Pr [12:0] Vertical pixel number of target image for preview DMA 0 PREVIEW DMA CONTROL REGISTER Register CIPRCTRL Address 0x48000080 R/W RW Description Preview DMA control related Reset Value 0 CIPRCTRL RGBburst1_Pr RGBburst2_Pr LastIRQEn_Pr Bit [23:19] [18:14] [2] Description Main burst length for preview RGB frames Remained burst length for preview RGB frames 1 : enable last IRQ at the end of frame capture 0 : normal Initial State 0 0 0 All burst lengths must be one of the 2,4,8,16. Example 1. Target image size : QCIF for RGB 32-bit format (horizontal width = 176 pixels. 1 pixel = 1 word) 176 pixel = 176 word. 176 % 16 = 0 main burst = 16, remained burst = 16 Example 2. Target image size : VGA for RGB 16-bit format (horizontal width = 640 pixels. 2 pixel = 1 word) 640 / 2 = 320 word. 21-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE 160 % 16 = 0 main burst = 16, remained burst = 16 Note: Preview path contains 640 pixel line buffer.(Codec path contains 2048 pixel line buffer) So, upper 1280 pixels, input images must be pre-scaled by over 1/2 for capturing valid preview image. PREVIEW PRE-SCALER CONTROL REGISTER 1 Register CIPRSCPRERATIO Address 0x48000084 R/W RW Description Preview pre-scaler ratio control Reset Value 0 CIPRSCPRERATIO SHfactor_Pr PreHorRatio_Pr PreVerRatio_Pr Bit [31:28] [22:16] [6:0] Description Shift factor for preview pre-scaler Horizontal ratio of preview pre-scaler Vertical ratio of preview pre-scaler Initial State 0 0 0 PREVIEW PRE-SCALER CONTROL REGISTER 2 Register CIPRSCPREDST Address 0x48000088 R/W RW Description Preview pre-scaler destination format Reset Value 0 CIPRSCPREDST PreDstWidth_Pr PreDstHeight_Pr Bit [27:16] [11:0] Description Destination width for preview pre-scaler Destination height for preview pre-scaler Initial State 0 0 PREVIEW MAIN-SCALER CONTROL REGISTER Register CIPRSCCTRL Address 0x4800008c R/W RW Description Preview main-scaler control Reset Value 0 CIPRSCCTRL Sample_Pr RGBformat_Pr Bit [31] [30] Description Sampling method for format conversion. (normally 1) 1 : 24-bit RGB , 0 : 16-bit RGB Initial State 0 0 21-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE ScaleUpDown_Pr [29:28] Scale up/down flag for preview scaler(In 1:1 scale ratio, this bit should be "1") 00 = down 11 = up 00 MainHorRatio_Pr PrScalerStart MainVerRatio_Pr [24:16] [15] [8:0] Horizontal scale ratio for preview main-scaler Preview scaler start Vertical scale ratio for preview main-scaler 0 0 0 PREVIEW DMA TARGET AREA REGISTER Register CIPRTAREA Address 0x48000090 R/W RW Description Preview pre-scaler destination format Reset Value 0 CIPRTAREA CIPRTAREA Bit [25:0] Description Target area for preview DMA = Target H size x Target V size Initial State 0 PREVIEW STATUS REGISTER Register CIPRSTATUS Address 0x48000098 R/W R Description Preview path status Reset Value 0 CIPRSTATUS OvFiCb_Pr OvFiCr_Pr FrameCnt_Pr FlipMd_Pr ImgCptEn_PrSC Bit [31] [30] [27:26] [24:23] [21] Description Overflow state of preview FIFO Cb Overflow state of preview FIFO Cr Frame count of preview DMA Flip mode of preview DMA Image capture enable of preview path Initial State 0 0 0 0 0 IMAGE CAPTURE ENABLE REGISTER Register CIIMGCPT Address 0x480000a0 R/W RW Description Image capture enable command Reset Value 0 CIIMGCPT Bit Description Initial State 21-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CAMERA INTERFACE ImgCptEn ImgCptEn_CoSc ImgCptEn_PrSc [31] [30] [29] camera interface global capture enable capture enable for codec scaler. This bit must be zero in scalerbypass mode. capture enable for preview scaler. This bit must be zero in scalerbypass mode. 0 0 0 Note: This register must be set at last. NOTES 21-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 VIDEO CODEC MPEG-4 VIDEO CODEC OVERVIEW MPEG-4 is an ISO/IEC standard developed by MPEG (Moving Picture Experts Group). MPEG-4 video aims at providing standardized core technologies allowing efficient storage, transmission and manipulation of video data in multimedia environments. MPEG-4 video codec of S3C24A0 provides high performance solution and lower the processing load of embedded processor core. The processing clock for DCT/quantization and motion estimation can be controlled by embedded processor core to reduce the power consumption. FEATURE ISO/IEC MPEG-4 Simple Profile @ Level 3 / ITU-T H.263 Base Line AMBA AHB Interface Real-time Encoding / Decoding Scalable image size : M x N macro-blocks up to 2048x2048 Hardware Accelerator for Motion Estimation, Motion Compensation, DCT/Quantization and VLC/VLD Unrestricted Mode & Advanced Prediction Mode (4MV) Half-pel Search Programmable Processing Clock in DCT/Quantization and Motion Estimation : HCLK ~ HCLK/30 22-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 VIDEO CODEC S3C24A0 RISC MICROPROCESSOR BLOCK DIAGRAM Figure 22-1 shows the functional block diagram of S3C24A0 MPEG-4 Video CODEC. This CODEC consists of four parts, i.e., DCT/Quantization, Motion Compensation, Motion Estimation and VLX(VLC/VLD). Qp factor curr mem DCT Q IQ IDCT mced mem DCT/Q recon mem COEF mem SDRAM SDRAM SDRAM MC VLX curr mem ME prev mem Figure 22-1. MPEG-4 Video CODEC Block Diagram 22-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION ESTIMATION MPEG-4 MOTION ESTIMATION OVERVIEW The MPEG-4 motion estimation block is a part of MPEG-4 Video CODEC. Motion estimation is an essential part in standard video coder such as H.26x, MPEG-1, MPEG-2 and MPEG-4. By removing temporal redundancies exiting in adjacent frames Advanced MRMCS (Multi-Resolution search using Multiple Candidates and Spatial correlation of motion field) algorithm is applied and it is based on the hierarchical search block-matching algorithm. FEATURE MPEG-4 Simple Profile @ Level 3 / H.263 Base Line AMBA AHB Interface Using Advanced MRMCS (Multi-Resolution search using Multiple Candidates and Spatial correlation of motion field) Algorithm Scalable image size : M x N macro-blocks up to 2048x2048 Unrestricted Mode & Advanced Prediction Mode (4MV) INTRA / INTER Mode Decision Macroblock-based Padding Search Range : [-16, 15.5] Half-pel Search Double Buffering of frame Data Re-use of Overlapped Search Range Data Variable processing clock ( HCLK ~ HCLK / 30 ) 23-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 MOTION ESTIMATION S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION ESTIMATION OPERATION BLOCK DIAGRAM Figure 23-1 shows the functional block diagram of MPEG-4 Motion Estimation. This block includes two parts with different clocks, i.e., system clock part and motion estimation clock part. internal_ctrl config interpolation sdram_ctrl data_arrange bsu shift_reg candidate sdram_read prev_mem (80x64x12) curr_mem (16x16x8x2) mode decision sram_write ME Clock Part System C lock Part Figure 23-1. MPEG-4 Motion Estimation Block Diagram sram_read 23-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION ESTIMATION OPERATION FLOW Firstly, set current, previous, and motion vector start address registers. Start address of previous frame must be considered the padding area. Set command register to operate motion estimation block. Current image data and padded previous image data of a macro-block are stored into the internal SRAM buffers from the external SDRAM. Operations to find motion vector of each macro-block are started after data transfer. After the completion of searches for each macro-block, the result data is written into the external SDRAM and then operations for one macro-block are finished. The operation unit in command register is set to decide the number of the macro-block to operate motion estimation continuously. Current Frame Start Address Y Image offset Y Image Previous Frame Start Address (a) Current Frame (b) Previous Frame Figure 23-2. Memory Map of Y (Luminance) Image for Current and Previous Frames Table 1. Example of Sizes of Y Image and Offset for QCIF and CIF Image Format Y Image Current Frame Previous Frame Offset QCIF 176x144 = 25,344 (176+16x2)x(144+16x2) = 36,608 (176+16x2)x16+16 = 3,344 CIF 352x288 = 101,376 (352+16x2)x(288+16x2) =122,880 (352+16x2)x16+16 = 6,160 23-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 MOTION ESTIMATION S3C24A0 RISC MICROPROCESSOR RESULT DATA The result of the motion estimation for each macro-block is stored into the external SDRAM area assigned in motion vector start address register. The result data of each macro-block is as follows. Block 0 Block 1 Address 0 1 2 3 4 MVY1 MVX1 MVY3 MVX3 SAD1 SAD3 SADinter MVY0 MVX0 MVY2 MVX2 SAD0 SAD2 INTRA/INTER Mode Block 2 Block 3 (a) Location of 8x8 block in one macro-block (b) Result data of one macro-block Figure 23-3. Motion Estimation Result Data MVX0, 1, 2, 3 and MVY0, 1, 2, 3 are X and Y components for motion vector of block 0, 1, 2, 3, respectively. The value of bit 0 of MVX0, 1, 2, 3 and MVY0, 1, 2, 3 indicates the value of half-pel unit. If this bit is 1, the value is 0.5. Otherwise, it indicates 0.0. Bit [7:1] is the signed number that is represented using 2's complement system. For example, if values of MVX0 and MVY0 are 0xE2 and 0x1B, respectively, the values of X and Y components of motion vector are -15.0 and 13.5, respectively. In the case of 4MV mode, motion vectors of 4 blocks are generated and in other cases, 4 motion vectors have the same value. SAD0, 1, 2 and 3 are the SAD values for each block and they can be used for DCT/Q skipping. The value of INTRA/INTER mode indicates that 0x0000 is INTER mode and 0xFFFF is INTRA mode. This value is only valid in case of MPEG-4 mode and always is 0x0000, that is, INTER mode in H.263 mode. SADinter is the result of min { SAD16, SAD8 } after half-pel operation and it is used for INTRA/INTER mode decision. 23-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION ESTIMATION MPEG-4 MOTION ESTIMATION SPECIAL REGISTERS Current Frame Start Address Register (ME_CFSA) Register ME_CFSA Address 0x4880_0000 R/W R/W Bit [31:0] Description Current frame start address register Description Set current frame start address Reset Value 0x0000_0000 Initial State 0x0000_0000 ME_CFSA Current frame start address Note 1. Current Frame Start Address is the start address of current Y image. Motion estimation operates only for Y (Luminance) image. Previous Frame Start Address Register (ME_PFSA) Register ME_PFSA Address 0x4880_0004 R/W R/W Bit [31:0] Description Previous frame start address register Description Set previous frame start address Reset Value 0x0000_0000 Initial State 0x0000_0000 ME_PFSA Previous frame start address Note 1. Previous Frame Start Address is the start address of previous Y image. Motion estimation operates only for Y (Luminance) image. 2. Previous Frame Start Address must be considered the padding area and it is the start address of the original previous image except the padding area. Motion Vector Start Address Register (ME_MVSA) Register ME_MVSA Address 0x4880_0008 R/W R/W Bit [31:0] Description Motion vector start address register Description Set motion vector start address Reset Value 0x0000_0000 Initial State 0x0000_0000 ME_MVSA Motion vector start address Note 1. Motion Vector Start Address is the start address to store the result data of motion estimation. 2. The number of the result data is determined according to the operation unit of command register. 23-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 MOTION ESTIMATION S3C24A0 RISC MICROPROCESSOR Command Register (ME_CMND) Register ME_CMND Address 0x4880_000C R/W R/W Bit [31:18] [17] [16] [15:4] [3] [2] [1] [0] Reserved 0 : round bit 0 1 : round bit 1 0 : 16x16 prediction mode 1 : advanced prediction mode (4MV) Reserved 0 : not active 1 : enable 0 : MPEG-4 mode 1 : H.263 mode 0 : not active 1 : enable 0 : not active 1 : clear Command register Description Description Reset Value 0x0000_0001 Initial State 0x0 0 0 0x0 0 0 0 1 ME_CMND Round control bit 4MV mode enable ME operation start bit MPEG-4/H.263 mode select Frame start bit Interrupt request clear bit Note 1. Frame start bit is enabled only when the first start of the frame. 2. ME operation start bit is enable every operation unit in the frame. 3. Interrupt request clear bit is cleared when ME operation start bit is enable at the same time. 23-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION ESTIMATION Status & S/W Reset Register (ME_STAT_SWR) Register ME_STAT_SWR Address 0x4880_0010 R/W R/(W) Bit [31:20] R [19:16] R [15:12] R [11:8] R [7] R [6:4] R [3:2] R [1] R/W [0] R Reserved BSU state buf FSM in candidate block Data flow FSM in internal_ctrl block BSU FSM in internal_ctrl block Reserved Control FSM in sdram_ctrl block Reserved 0 : set S/W reset 1 : clear S/W reset 0 : idle 1 : busy Description Status & S/W reset register Description Reset Value 0x0000_0002 Initial State 0x0 0x0 0x0 0x0 0 0x0 0x0 1 0 ME_STAT_SWR Reserved BSU state buf FSM Data flow FSM BSU FSM Reserved Control FSM Reserved S/W reset bit Motion estimation status bit Note 1. In case of not using interrupt, motion estimation operation must be started when motion estimation status bit is "0". 2. S/W reset bit is used to reset motion estimation block. It reset special registers and internal finite state machines. 3. Since S/W reset bit keeps the written value until written into "0" or hardware reset, be careful to use S/W reset bit. 23-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 MOTION ESTIMATION S3C24A0 RISC MICROPROCESSOR Configuration Register (ME_CNFG) Register ME_CNFG Address 0x4880_0014 R/W R/W Bit [31:25] [24] [23] [22:16] [15:14] [13:0] Reserved 0 : disable 1 : enable Reserved Threshold value to be compared to the intensity variation in the fast mode Reserved The number of macro-blocks to operate motion estimation continuously Description Configuration register Description Reset Value 0x0010_0063 Initial State 0x0 0 0 0x10 0x0 0x0063 ME_CNFG Fast mode enable bit Threshold value Operation unit Note 1. The operation unit is variable only inside one frame. 2. In fast mode, the execution time is considerably reduced with less PSNR. 3. Fast mode enable bit is only valid in case of MPEG-4 mode. In H.263 mode, this bit always is not enabled. Image Format Register (ME_IMGFMT) Register ME_IMGFMT Address 0x4880_0018 R/W R/W Bit [31:15] Reserved [14:8] [7] [6:0] The number of vertical macro-blocks minus one Reserved The number of horizontal macro-blocks minus one Description Image format register Description Reset Value 0x0000_080A Initial State 0x0 0x08 0 0x0A ME_IMGFMT N value M value 23-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION COMPENSATION MPEG-4 MOTION COMPENSATION OVERVIEW The MPEG-4 motion compensation block is a part of MPEG-4 Video CODEC. Motion compensation is a key element in the inter compression. In inter compression pixels in a region of a previous frame are used to predict pixels in a region of the current frame. Differences between the previous frame and the mced frame are then coded to whatever accuracy is affordable at the desired bit-rate. FEATURE MPEG-4 Simple Profile @ Level 3 / H.263 Base Line AMBA AHB Interface 8x8 Block-based Motion Compensation Scalable image size : M x N macro-blocks up to 2048x2048 Dedicated DMA Unrestricted Mode & Advanced Prediction Mode (4MV) Search Range : [-32, 31.5] Half-pel Search Error Concealment Support Encoding / Decoding 24-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 MOTION COMPENSATION S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION COMPENSATION OPERATION BLOCK DIAGRAM Figure 24-1 shows the functional block diagram of MPEG-4 Motion Compensation. regs motionvector control addr_gen fifo Figure 24-1. MPEG-4 Motion Compensation Block Diagram 24-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION COMPENSATION OPERATION FLOW Firstly, set Y/Cb/Cr start address registers of current and previous. Each start address of current and previous frames must be considered the padding area. Secondly, set motion vector start address register. Set command register to operate motion compensation block. The operation unit in command register is set to decide the number of the macro-block to motion compensation continuously. The operation of motion compensation is as follows. Start -> Motion Vector Read -> Data Read -> Data Processing -> Data Write Motion compensation is operated in 8x8 block unit. Motion compensation cannot support the encoding and the decoding at the same time. Current and previous frame are padded frames. Y offset Y Image Y Image Original Frame Cb Start Address Cb Image Original Frame Cr Start Address Cr Image Padded Frame Cb Start Address Padded Frame Cr Start Address Cb offset Cb Image Cr offset Cr Image Original Frame Y Start Address Padded Frame Y Start Address (a) Original Frame (b) Padded Frame Figure 24-2. Y/Cb/Cr Image Memory Map of Original and Padded Frames Table 1. Sizes of Y/Cb/Cr Image and Offset for QCIF and CIF QCIF Original Frame Padded Frame Offset Y Cb/Cr Y Cb/Cr Y Cb/Cr 176x144 = 25,344 88x72 = 6,336 (176+16x2)x(144+16x2) = 36,608 (88+8x2)x(72+8x2) = 9,152 (176+16x2)x16+16 = 3,344 (88+8x2)x8+8 = 840 CIF 352x288 = 101,376 176x144 = 25,344 (352+16x2)x(288+16x2) = 122,880 (176+8x2)x(144+8x2) = 30,720 (352+16x2)x16+16 = 6,160 (176+8x2)x8+8 = 1,544 24-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 MOTION COMPENSATION S3C24A0 RISC MICROPROCESSOR CONFIGURATION OF QCIF / CIF FRAME 176 88 144 QCIF Y 72 QCIF Cb/Cr 352 176 288 CIF Y 144 CIF Cb/Cr Figure 24-3. Y/Cb/Cr Configuration for QCIF/CIF Original Frame 176 + 32 = 208 176 88 + 16 = 104 88 144 + 32 = 176 144 QCIF Y 72 + 16 = 88 72 QCIF Cb/Cr 352 + 32 = 384 352 176 + 16 = 192 176 288 + 32 = 320 288 CIF Y 144 + 16 = 160 144 CIF Cb/Cr Figure 24-4. Y/Cb/Cr Configuration for QCIF/CIF Padded Frame 32-bit 5 x 396 = 1980 32-bit 5 x 99 = 495 QCIF MV CIF MV 24-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION COMPENSATION Figure 24-5. Motion Vector Configuration for QCIF/CIF Image MPEG-4 MOTION COMPENSATION SPECIAL REGISTERS Previous Frame Y Start Address Register for the Encoder (MC_PFYSA_ENC) Register MC_PFYSA_ENC Address 0x48C0_0000 R/W R/W Bit [31:0] Description Previous frame Y start address register (ENC) Description Set previous frame Y start address (ENC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_PFYSA_ENC Previous frame Y start address (ENC) MCed Frame Y Start Address Register for the Encoder (MC_MFYSA_ENC) Register MC_MFYSA_ENC Address 0x48C0_0004 R/W R/W Bit [31:0] Description MCed frame Y start address register (ENC) Description Set MCed frame Y start address (ENC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_MFYSA_ENC MCed frame Y start address (ENC) Previous Frame Y Start Address Register for the Decoder (MC_PFYSA_DEC) Register MC_PFYSA_DEC Address 0x48C0_0008 R/W R/W Bit [31:0] Description Previous frame Y start address register (DEC) Description Set previous frame Y start address (DEC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_PFYSA_DEC Previous frame Y start address (DEC) MCed Frame Y Start Address Register for the Decoder (MC_MFYSA_DEC) Register MC_MFYSA_DEC Address 0x48C0_000C R/W R/W Bit [31:0] Description MCed frame Y start address register (DEC) Description Set MCed frame Y start address (DEC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_MFYSA_DEC MCed frame Y start address (DEC) 24-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 MOTION COMPENSATION S3C24A0 RISC MICROPROCESSOR Previous Frame Cb Start Address Register for the Encoder (MC_PFCbSA_ENC) Register MC_PFCbSA_ENC Address 0x48C0_0010 R/W R/W Bit [31:0] Description Previous frame Cb start address register (ENC) Description Set previous frame Cb start address (ENC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_PFCbSA_ENC Previous frame Cb start address (ENC) Previous Frame Cr Start Address Register for the Encoder (MC_PFCrSA_ENC) Register MC_PFCrSA_ENC Address 0x48C0_0014 R/W R/W Bit [31:0] Description Previous frame Cr start address register (ENC) Description Set previous frame Cr start address (ENC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_PFCrSA_ENC Previous frame Cr start address (ENC) MCed Frame Cb Start Address Register for the Encoder (MC_MFCbSA_ENC) Register MC_MFCbSA_ENC Address 0x48C0_0018 R/W R/W Bit [31:0] Description MCed frame Cb start address register (ENC) Description Set MCed frame Cb start address (ENC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_MFCbSA_ENC MCed frame Cb start address (ENC) MCed Frame Cr Start Address Register for the Encoder (MC_MFCrSA_ENC) Register MC_MFCrSA_ENC Address 0x48C0_001C R/W R/W Bit [31:0] Description MCed frame Cr start address register (ENC) Description Set MCed frame Cr start address (ENC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_MFCrSA_ENC MCed frame Cr start address (ENC) 24-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION COMPENSATION Previous Frame Cb Start Address Register for the Decoder (MC_PFCbSA_DEC) Register MC_PFCbSA_DEC Address 0x48C0_0020 R/W R/W Bit [31:0] Description Previous frame Cb start address register (DEC) Description Set previous frame Cb start address (DEC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_PFCbSA_DEC Previous frame Cb start address (DEC) Previous Frame Cr Start Address Register for the Decoder (MC_PFCrSA_DEC) Register MC_PFCrSA_DEC Address 0x48C0_0024 R/W R/W Bit [31:0] Description Previous frame Cr start address register (DEC) Description Set previous frame Cr start address (DEC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_PFCrSA_DEC Previous frame Cr start address (DEC) MCed Frame Cb Start Address Register for the Decoder (MC_MFCbSA_DEC) Register MC_MFCbSA_DEC Address 0x48C0_0028 R/W R/W Bit [31:0] Description MCed frame Cb start address register (DEC) Description Set MCed frame Cb start address (DEC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_MFCbSA_DEC MCed frame Cb start address (DEC) MCed Frame Cr Start Address Register for the Decoder (MC_MFCrSA_DEC) Register MC_MFCrSA_DEC Address 0x48C0_002C R/W R/W Bit [31:0] Description MCed frame Cr start address register (DEC) Description Set MCed frame Cr start address (DEC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_MFCrSA_DEC MCed frame Cr start address (DEC) 24-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 MOTION COMPENSATION S3C24A0 RISC MICROPROCESSOR Motion Vector Start Address Register for the Encoder (MC_MVSA_ENC) Register MC_MVSA_ENC Address 0x48C0_0030 R/W R/W Bit [31:0] Description Motion vector start address register (ENC) Description Set motion vector start address (ENC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_MVSA_ENC Motion vector start address (ENC) Motion Vector Start Address Register for the Decoder (MC_MVSA_DEC) Register MC_MVSA_DEC Address 0x48C0_0034 R/W R/W Bit [31:0] Description Motion vector start address register (DEC) Description Set motion vector start address (DEC) Reset Value 0x0000_0000 Initial State 0x0000_0000 MC_MVSA_DEC Motion vector start address (DEC) 24-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION COMPENSATION Command Register (MC_CMND) Register MC_CMND Address 0x48C0_0038 R/W R/W Bit [31:18] Reserved [17] [16:7] [6] [5] [4] [3:2] [1] [0] 0 : round bit 0 1 : round bit 1 Reserved 0 : Decoder 1 : Encoder 0 : not active 1 : enable 0 : not active 1 : enable Reserved 0 : not active 1 : enable Reserved Command register Description Description Reset Value 0x0000_0040 Initial State 0x0 0 0x0 1 0 0 0x0 0 0 MC_CMND Rounding control bit Encoder / Decoder mode select Interrupt request clear bit MC operation start bit MC abort bit - Note 1. MC operation start bit is enabled every operation unit in the frame. 2. Interrupt request clear bit is cleared when MC operation start bit is enabled at the same time. 3. MC abort bit has the same function as S/W reset bit of Status & S/W Reset Register and is cleared automatically. 24-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 MOTION COMPENSATION S3C24A0 RISC MICROPROCESSOR Status & S/W Reset Register (MC_STAT_SWR) Register MC_STAT_SWR Address 0x48C0_003C R/W R/(W) Bit [31:9] R [8:4] R [3:2] R [1] R/W [0] R Reserved Control FSM in control block Reserved 0 : set S/W reset 1 : clear S/W reset 0 : idle 1 : busy Description Status & S/W reset register Description Reset Value 0x0000_0002 Initial State 0x0 0x0 0x0 1 0 MC_STAT_SWR Control FSM S/W reset bit Motion compensation status bit Note 1. In case of not using interrupt, motion compensation operation must be started when motion compensation status bit is "0". 2. S/W reset bit is used to reset motion compensation block. It reset special registers and internal finite state machines. 3. Since S/W reset bit keeps the written value until written into "0" or hardware reset, be careful to use S/W reset bit. 24-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 MOTION COMPENSATION Configuration Register (MC_CNFG) Register MC_CNFG Address 0x48C0_0040 R/W R/W Bit [31] 0 : disable 1 : enable Reserved Description Configuration register Description Reset Value 0x0000_0063 Initial State 0 0x0 0 0x0 0x0 0x0063 MC_CNFG MC X, Y count update enable bit MC Y count update value MC X count update value Operation unit [30:24] Update value when bit 31 is set to "1" [23] [22:16] Update value when bit 31 is set to "1" [15:14] Reserved [13:0] The number of the macro-block to operate motion compensation continuously Note 1. The operation unit is variable only inside one frame. 2. MC X, Y count update enable bit and MC X, Y count update value should be written at the same time to operate motion compensation for specific macro-blocks in the frame.. 24-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MPEG-4 MOTION COMPENSATION S3C24A0 RISC MICROPROCESSOR Image Format Register (MC_IMGFMT) Register MC_IMGFMT Address 0x48C0_0044 R/W R/W Bit [31:15] Reserved [14:8] [7] [6:0] The number of vertical macro-blocks minus one Reserved The number of horizontal macro-blocks minus one Description Image format register Description Reset Value 0x0000_080A Initial State 0x0 0x08 0 0x0A ME_IMGFMT N value M value 24-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ MPEG-4 DCTQ (PRELIMINARY) OVERVIEW This specification defines the DCT, IDCT, Quantisation and Dequantisation engine for MPEG-4 codec (refer Figure 25-1). MPEG-4 DCTQ engine gets current macroblock, previous macroblock and quantisation information from main memory. After internal DCTQ operation, this engine writes quantized coefficients and reconstructed macroblock to main memory. Using quantisation factor, it is possible to control bit-rate for video streams. Padding operation for motion estimation supports on the writing reconstruction macroblock. Also, it is possible to setting intra or inter mode and Qp value with accessing quantisation information in memory. This engine has own DMA module. So, just by setting function attributes into DCTQ SFR (Special Function Register), this engine automatically performs DCT, IDCT, Quantisation, Dequantisation, and memory access. MPEG-4 DCTQ Current MB Local Mem. DCT Q-inform SDRAM Q SDRAM Level Local Mem. SDRAM IQ IDCT Reference MB Local Mem. Reconstruct MB Local Mem. SDRAM MC SDRAM Q/IQ skip mode ME Figure 25-1. DCTQ overview 25-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ FEATURES -- H.263, MPEG-4 simple profile level 0,1,2 3 supports. -- DCT / IDCT / Q / IQ operations -- Residual extraction / Image reconstruction -- Padding operation for unrestricted motion compensation -- Rate control by Q-inform -- Intra refresh feasibility by Q-inform -- Dedicated DMA -- MPEG-4 encoder/decoder support -- JPEG DCT/IDCT support -- Variable aspect ratio and size (up to 4096 x 4096) TIMING DIAGRAM DCTQ IP operates by OPUNIT. OPUNIT is a macroblock-based, which is 16x16 pixel array. One macroblock consists of six 8x8 block, which are 4 luminance blocks and, 2 chrominance blocks. DCTQ IP starts with DCTQ_START signal by register setting. And, during operation, DCTQ_BUSY signal remains High. After dctq operation, IRQ is generated. And then, DCTQ_BUSY signal go to Low. CPU can read the state of DCTQ by referencing DCTQ_BUSY. In this document, for convenience, dctq operation means dct, quantisation, dequantisation and, inverse dct operations. HCLK DCTQ_START DCTQ_BUSY IRQ STATE DCT/Q/IQ/IDCT operating period by OPUNIT MB Figure 25-2. DCTQ operation timing diagram 25-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ SEPARATED CLOCK DOMAIN DCTQ IP has two clock domains. The one is a system bus clock domain. And, the other is a DCTQ core clock domain. These two clock domains are independent. However, it is recommended to use integer number division for DCTQ core clock. For low power consumption, if possible, lower DCTQ core clock is requested within codec performance. PLL Divide Counter System bus clock Divide Counter 1/1 ~ 1/30 DCTQ core clock DCT/Q IQ/IDCT Figure 25-3. DCTQ clock domain DCT A separable 2-dimensional Discrete Cosine Transform (DCT) is used. N -1 N -1 ( 2 x + 1)u ( 2 y + 1) v 2 F (u, v ) = C (u) C (v ) f ( x , y ) cos cos N 2N 2N x=0 y=0 C (u), C ( v ) = 1 for u,v = 0 2 otherwise =1 In this IP, N value is fixed to 8. Before quantisation, F(u,v) is rounded. For reducing multiplication and reducing hardware size, row-column decomposition and Chen's algorithm is used. IDCT Inverse DCT module follows next equation. 2 f ( x, y) = N C(u)C(v) F (u, v) cos u=0 v=0 N -1 N -1 ( 2 x + 1)u ( 2 y + 1) v cos 2N 2N 25-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ QUANTISATION The Quantisation parameter Qp takes integer values from 1 to 31. The quantisation stepsize is 2xQp. COF LEVEL COF' A transform coefficient to be quantized. Absolute value of the quantized version of the transform coefficient. Reconstructed transform coefficient. INTRA DC (In MPEG-4 mode) LEVEL = COF // dc_scaler Others For INTRA: LEVEL = |COF| / (2xQp) For INTER: LEVEL = (|COF| - Qp/2) / (2xQp) Clipping to [-127:127] is performed for all coefficients except intra DC. The sign of COF is then added to obtain COF' : COF' = Sign(COF) x |COF| DEQUANTISATION INTRA DC (In MPEG-4 mode) COF' = LEVEL x dc_scaler Others |COF'| = 0, if LEVEL = 0 |COF'| = 2 x Qp x LEVEL + Qp, if LEVEL 0, Qp is odd |COF'| = 2 x Qp x LEVEL + Qp - 1, if LEVEL 0, Qp is even Clipping is [-2048:2047] is performed before IDCT. 25-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ FRAME MEMORY MAP The frame memories for DCTQ are shown in figure 1-4. The padding area of reference frame fixed to 16 pixel extensions from original image to outsides in any other image sizes. Because of DCTQed bits per pixel, the DCTQed frame memory size is double compared to original frame size. Show the bit format in figure 1-6. Qinformation frame consists of the words of Q-information by macroblock units. 176 Start address location of register 88 88 Current frame memory size QCIF Y 144 QCIF Cb 72 QCIF Cr 72 208 176 Start address location of register 104 88 104 88 Reference frame memory size QCIF Y Padding area 144 176 QCIF Cb 72 88 QCIF Cr 72 88 352 Start address location of register 176 176 DCTQed frame memory size QCIF Y 144 QCIF Cb 72 QCIF Cr 72 word Start address location of register Q-information frame memory size Qinform 99 Current frame memory size = (176x144) + (88x72) + (88x72) = 38016 Bytes Reference frame memory size = (208x176) + (104x88) + (104x88) = 54912 Bytes DCTQed frame memory size = (352x144) + (176x72) + (176x72) = 76032 Bytes Q-inform memory size = 4 x 99 = 396 Bytes Figure 25-4. DCTQ frame memory map in QCIF case 25-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ Q-INFORMATION After DCTQ register setting, the first step of operations is the read of Q-information for macroblock. The DCTQ engine observes the Q-information and then determines the intra- or inter-modes, MB skip mode and, pick up Quantisation information. For CBP mode in the decoder, software has to write zero coefficients into the each skipped 8x8 blocks. In MB-skip case that is not_coded(Inter, zero-MV), in the decoder, DCTQ operation can be skipped for next MB operation. This MB-skip mode is not recommended with VLC in the encoder. MSB 31 Reserved 12 11 Intra/ Inter 10 Qp step 6 5 MB skip inform LSB 0 1 = Intra MB 0 = Inter MB 31 Quantization step size (1 ~ 31) 6'b111111 = MB skip 6'b000000 = Normal Figure 25-5. Q-information structure 25-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ BIT FORMAT The DMA operations are performed with word units. Internal memory accesses are mainly byte based. The dctq operations use the 9, 12 bits. Only little endian is supported in the words. Q-info 5-bit Word 8-bit 8-bit 8-bit 8-bit 1) Word 12-bit CURLM 8-bit - 9-bit 8-bit DCT 12-bit Q 12-bit DCTQ LM s Word 12-bits s 11-bit 16-bits 32-bits s 12-bits s 11-bit 16-bits 32-bits MCDLM IQ 12-bit IDCT 8-bit 9-bit + 8-bit RECLM Word 8-bit 8-bit 8-bit 8-bit 8-bit Word 8-bit 8-bit 8-bit 32-bits 32-bits CURLM : Current MB local sram, MCDLM : MCed MB local sram, DCTQLM: DCTQed MB local sram, RECLM : Reconstructed MB local sram 1) View the Q-inform structure in figure 1-5. Figure 25-6. DCTQ bit-format Output bit-format of coefficient is incompatible with 2's compliment for software. For getting sign, check the MSB of output coefficient. And, lower 12-bits are levels for VLC. For block skip mode in decoder, software can put the `0' coefficients into coefficient memory. In inter-mode, this zero residuals add by MCed pixels for reconstruction image. 25-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ TRANSPOSED COEFFICEINT OUTPUT The coefficient outputs of DCTQ are transposed in 8x8 block. One coefficient is stored into the half word. In memory, the sequences of coefficient are 0-8-16-24- etc. In macroblock level, the output sequence of 6 blocks are as shown in below diagram. Transposed block 32-bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Y Blocks 1 3 2 4 C Blocks 5 6 31 62 63 16 15 0 8 24 40 56 . . . 9 25 41 57 . . . . . . 0 16 32 48 0x20000000 0x20000004 0x20000008 0x2000000C address offset (1 line) SDRAM Memory Map 1 17 33 49 0x20000058 0x2000005C 0x20000060 0x20000064 Figure 25-7. Transposed coefficient output for MB 25-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ SOFTWARE INTERFACE This MPEG-4 DCTQ provides a generic data-exchange method. It is recommended that the CONTROL register should be set at the last SFR setting sequence. MPEG-4 DCTQ SPECIAL REGISTERS CURRENT FRAME Y START ADDRESS REGISTER Register SAYCF Address 0x4900_0000 R/W RW Description Current frame luminance start address Reset Value 0x00000000 SAYCF SAYCF Bit [31:0] Description These bits indicate the luminance start address of current frame. Initial State 0x00000000 CURRENT FRAME CB START ADDRESS REGISTER Register SACBCF Address 0x4900_0004 R/W RW Description Current frame Cb start address Reset Value 0x00000000 SACBCF SACBCF Bit [31:0] Description These bits indicate the chrominance Cb start address of current frame. Initial State 0x00000000 CURRENT FRAME CR START ADDRESS REGISTER Register SACRCF Address 0x4900_0008 R/W RW Description Current frame Cr start address Reset Value 0x00000000 SACRCF SACRCF Bit [31:0] Description These bits indicate the chrominance Cr start address of current frame. Initial State 0x00000000 25-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ REFERENCE FRAME Y START ADDRESS REGISTER Register SAYRF Address 0x4900_000C R/W RW Description Reference frame luminance start address Reset Value 0x00000000 SAYRF SAYRF Bit [31:0] Description These bits indicate the luminance start address of reference frame. Initial State 0x00000000 REFERENCE FRAME CB START ADDRESS REGISTER Register SACBRF Address 0x4900_0010 R/W RW Description Reference frame Cb start address Reset Value 0x00000000 SACBRF SACBRF Bit [31:0] Description These bits indicate the chrominance Cb start address of reference frame. Initial State 0x00000000 REFERENCE FRAME CR START ADDRESS REGISTER Register SACRRF Address 0x4900_0014 R/W RW Description Reference frame Cr start address Reset Value 0x00000000 SACRRF SACRRF Bit [31:0] Description These bits indicate the chrominance Cr start address of reference frame. Initial State 0x00000000 DCTQED FRAME Y START ADDRESS REGISTER Register SAYDQF Address 0x4900_0018 R/W RW Description DCTQed frame luminance start address Reset Value 0x00000000 SAYDQF SAYDQF Bit [31:0] Description These bits indicate the luminance start address for storing DCT and Quantized outputs. Initial State 0x00000000 25-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ DCTQED FRAME CB START ADDRESS REGISTER Register SACBDQF Address 0x4900_001C R/W RW Description DCTQed frame Cb start address Reset Value 0x00000000 SACBDQF SACBDQF Bit [31:0] Description These bits indicate the chrominance Cb start address for storing DCT and Quantized outputs. Initial State 0x00000000 DCTQED FRAME CR START ADDRESS REGISTER Register SACRDQ F Address 0x4900_0020 R/W RW Description DCTQed frame Cr start address Reset Value 0x00000000 SACRDQF SACRDQF Bit [31:0] Description These bits indicate the chrominance Cr start address for storing DCT and Quantized outputs. Initial State 0x00000000 QUANTISATION FACTOR START ADDRESS REGISTER Register SAQP Address 0x4900_0024 R/W RW Description Qp start address Reset Value 0x00000000 SAQP SAQP Bit [31:0] Description These bits indicate the Qp start address for Quantisation informations. Initial State 0x00000000 25-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ IMAGE SIZE REGISTER Register IMGSIZE Address 0x4900_0028 R/W RW Description Image horizontal and vertical pixel number Reset Value 0x00000000 Because DCTQ engine operates by macroblock unit, the horizontal and vertical pixel numbers should be the multiple of 16. For example, you can extract the exact SVGA image size after 800x608 dctq operation with dummy pixels. IMGSIZE Image_X Image_Y Description [28:16] Image horizontal pixel number [12:0] Image vertical pixel number Bit Initial State 0 0 SH Q REGISTER Register SHQ Address 0x4900_002C R/W RW Description Short header quantization mode Reset Value 0x00000000 SHQ Is_SHQ Bit [27] Description 0 : MPEG-4 dc_scaler Q-mode for Intra-DC 1 : Short header Q-mode (/8,*8) for Intra-DC Initial State 0 Reserved [26:0] Must be zero 0 Reserved SFR 0x49000030 CONTROL REGISTER Register DCTQCTRL Address 0x4900_0034 R/W RW Description Control register Reset Value 0x00000000 DCTQCTRL Reserved Coeff_not_write Bit [31:30] Reserved [29] Description Initial State 0 0 Coefficients write operation to memory can be skipped with VLC IP `On' state. In this case, DCTQ engine write the coefficient to the internal memory of VLC directly. DCTQ operates by MB-unit with watching VLC operation (BUSY). In decoder mode, this bit must be zero. If only DCTQ is operating, With_VLC [28] 0 25-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MPEG-4 DCTQ this bit should be zero. DCT_only IDCT_only SWRST OPUNIT [27] [26] [25] [24:8] Quantization skip for JPEG mode De-quantization skip for JPEG mode This bit indicates the software reset of MPEG-4 DCTQ. These bits controls the number of DCTQ operations by macroblock unit. If these bits are 14'd99 in QCIF size, DCTQ operates during one frame without command. This bit indicates the busy state of DCTQ. 1 = DCTQ is operating. 0 = DCTQ is not operating. DCTQST [6] This bit indicates the start of DCTQ operation. This bit is autocleared. Reserved This bit indicates that the format of current DCTQ operation is H.263 or not. 1 = H.263 (without padding) 0 = MPEG-4 (with padding) Reserved ISENC [3] [2] Reserved This bit indicates that the current DCTQ operation is encoding or not. 1 = encoding 0 = decoding Reserved FRST [1] [0] Reserved This bit indicates the frame start signal, which is active only first OPUNIT. 1 = frame start 0 = normal 0 0 0 0 0 0 0 0 0 DCTQBSY [7] 0 Reserved ISH263 [5] [4] 0 0 Reserved SFR 0x49000038 Reserved SFR 0x4900003c NOTES * It is needed for software-reset to convert from encoder to decoder or from decoder to encoder. 25-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR VLX VLX (Preliminary) OVERVIEW VLX module consist of VLC( Variable Length Coding )and VLD( Variable Length Decoding ) module. VLC block does the entropy coding in MPEG4 system. It assigns small bits to a symbol that occurs frequently in the source data. On the other hand, it assigns large bits to a symbol that occurs rarely. As a result, the size of the coded data is smaller than that of the original. MPEG4 used a predefined table that assigns a code to each symbol (RUN, LEVEL, LAST ) and cannot be redefined by the user in MPEG4 simple profile. VLC received coefficient data and control signal from DCTQ h/w module. So SFR control bits must be set same value in DCTQ module SFR data in VLC mode. VLD block does the entropy decoding in MPEG4 system. It reads the coded bit stream from the main memory, extracts one code from the coded bit stream, and generates the symbol from the extracted code. As the length of a code is variable, VLD block searches the coded bit stream step by step and compares the intermediate code value with the code table to get a complete code value. VLD module is only 1 macro block operation so that always need to control interface between CPU. S/w must to be known the time of end of MB, so polling or interrupt signal generation in VLD h/w. VLC and VLD operation are not supported operation simultaneous. If intra macro block in VLD mode need to DC prediction decoding and inverse scanning to use in DCTQ H/W module. And inter block in VLD mode don't need extra operation to use DCTQ module. VLX module designed for AMBA2.0 and has two dedicated DMA, and 1 master and 1 slave AHB interface. FEATURE MPEG-4 Simple Profile AMBA AHB Interface Use Dedicated DMA Programmable Image size QCIF, CIF, VGA, QVGA etc. Include DC prediction in VLC mode.. Interrupt and polling mode supported Support MPEG4 simple profile basic table excluding reversible VLC table 26-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 VLX S3C24A0 RISC MICROPROCESSOR MPEG-4 VLX( Variable Length Coding, Decoding ) OPERATION DCTQ AHB I/F External MEM. I/F AHB ctrl. I/F coeff I/F VLX AHB master I/F VLX Ctrl. Coeff Mem. VLC path VLD path AHB slave I/F Figure 26-1 VLX top interface block diagram VLC VLC block has 3 major blocks to code the input symbols. They are VLC coder, run-length coding (RLC), DC prediction blcok. Run-Length Coder(RLC). The output of the zigzag address generator is the sequence of the DCT coefficients that read in zigzag order or DCTQ zigzag order . These coefficients are coded to RLC. RLC coder result is LAST, RUN, LEVEL value. In MPEG4 mode, the AC coefficients are coded to 3-D RLC code: (LAST, RUN,LEVEL). RUN is the zero number before the non-zero value, LEVEL. The LAST indicates that the LEVEL is the last non-zero value in the DCT block. RLC coder searched the 8x8 blocks of transform coefficients are scanned with "zigzag" scanning. Zigzag order is explained Figure. 26-2 26-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR VLX 1 3 4 10 11 21 22 36 2 5 9 12 20 23 35 37 6 8 13 19 24 34 38 49 7 14 18 25 33 39 48 50 15 17 26 32 40 47 51 58 16 27 31 41 46 52 57 59 28 30 42 45 53 56 60 63 29 43 44 54 55 61 62 64 Figure 26-2 ZigZag scanning method A three dimensional variable length coder is used to code transform coefficients. An EVENT is a combination of three parameters LAST RUN LEVEL 0 : There are more nonzero coefficients in the block. 1 : This is the last nonzero coefficient in the block. Number of zero coefficients preceding the current nonzero coefficient. Magnitude of the coefficient. The most commonly occurring combinations of LAST, RUN, LEVEL are coded with variable length codes given standard table. The remaining combinations, no matched case in table use three ESCAPE mode coding. First, Level vaule change Level minus Lmax( Lmax is defined by RUN . Second, RUN value change RUN minus Rmax ( Rmax is defined by Level ). Last, FLC, fixed length coding, are coded with a 22 bit word fixed length coding consisting of ESCAPE( 7 bit ), LAST(1 bit ), RUN( 6 bit ),LEVEL(8 bit), coding used. Entropy coder Entropy coding is performed after the run-length coding. MPEG4 in simple profile uses a predefined table that gives the code and the length of the code for each symbol. Entropy coder use many predefined table, DC table, intra luminance table, intra chrominance table, various escape table. Etc.. . So, the table in MPEG4 can be fixed in hardware to speed up the entropy coding using direct matching method. it supports only the MPEG4 simple profile, the table is hardwired to speed up the VLC and to lower the power consumption. DC prediction coder VLC support DC prediction operation. but AC prediction is not supported VLX module. So scanning method is always zigzag scanning. DC prediction value calculates below fomular. Assume, `X', `A', `B' and `C' correspondingly refer to the current block, the previous block, the block above and to the left, and the block immediately above as shown. 26-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 VLX S3C24A0 RISC MICROPROCESSOR B or A C or X D Y Macroblock Figure 26-3 Previous neighboring blocks used in DC prediction The differential DC is then obtained by subtracting the DC prediction, DCX' from DC of block `X'. if (|DCA - DCB| < |DCB - DCC|) else DCX = DCX - DCX' DCX' = DCC DCX' = DCA DC prediction h/w support Q-step Scaling method. Q-step scaling method is To compensate for differences in the quantisation of previous horizontaly adjacent or vertically adjacent blocks used in AC prediction of the current block, scaling of prediction coefficients becomes necessary. Thus the prediction is modified so that the predictor is scaled by the ratio of the current quantisation stepsize and the quantisation stepsize of the predictor block. VLC mode operations sequence. Receiving the data and control signal from the DCTQ H/W module. 1 macro block data, zigzag ordered data receive form DCTQ module and data save COEF_MEM in the VLX H/W module. SFR control bits already must be set. The value, after run-length coding, is coded with intra, Inter, escape run, escape level , dc code table, and then saved external memory. VLC output save external memory on 1 word value. Not coded information, from MSB to LSB data. {word count(16bit), bit count(16bit) }, VLC coeff. ordered save.VLX output in VLC mode are CBP information, Word count, Bit count VLCed stream data. Figure 26-4 show the output format in VLC mode. CBP information : Coded Block Pattern explain MB data exist or not . if Coded Block Patter value 1 , that component has no DCTQ coefficient data. One MB has six block so CBP information is six bit output. 0 bit is y0 block and 5 bit is Cr block. Figure 26-4 show the CBP bit information. 26-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR VLX External Memory VLCed Addr Word count VLC stream . Big-endian value . . CBP Bit count First MB data 128word( offset ) . . . VLCed Addr + (128*4) Word count Word count VLC stream . . . CBP Bit count Second MB data Bit count CBP value . . . 1MB = 6 block CR Cb y3 y2 y1 y0 Figure 26-4 VLC output bit stream format Output of encoder, saved data in memory, is big-endian data Interrupt signal or busy signal generated by end of OP_UNIT processing. Interrupt signal generation can be controlled by INT_ENABLE bit. Busy signal put to DCTQ module and be set SFR bit. HCLK Write_start ( from DCTQ ) VLX_BUSY VLX_IRQ STATE DCTQ coeff. writting period VLXoperating period by one MB Figure 26-5 VLC start, busy, and Interrupt signal timing diagram. At the VOP layer, intra_dc_vlc_thr allows switching between DC Intra VLC and AC Intra VLC when coding DC coefficients of Intra macroblocks. When the intra AC-VLC is turned on, INTRA-DC transform coefficients are not handled separately any more, but treated the same as all AC coefficients. That means a zero INTRA-DC will not be coded but will simply increase the run for the following AC-coefficients. But this H/W set intra_dc_thr value fixed zero value, so always threated DC coefficients. 26-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 VLX S3C24A0 RISC MICROPROCESSOR VLD VLD h/w support only coefficient bit stream variable length decoding. Except header decoding, intra DC/AC inverse prediction. so VLD h/w need to communicate to S/W per macro block. This operation show Figure 266. 31 BIT_SADDR 0 START_BIT_CNT 16 31 0 Big-endian data Bit stream VLC_EADDR 0 END_BIT_CNT 31 Figure 26-6 VLD bit stream h/w and S/W interface format. S/W must be set BIT_SADDR and START_BIT_CNT and bitstream data. BIT_SADDR is address of start coefficient bit stream. And START_BIT_CNT is start bit of current macro block bit stream. And bitstream data must be big-endian data. VLD h/w generate VLC_EADDR and END_BIT_CNT value after macro block VLD operation. Before next macro block start s/w have to find BIT_SADDR and START_BIT_CNT after header parsing and VLD. Decoded coefficient data saved external memory Y image, Cb image, and Cr image. Figure 26-7 is example external memory amount. So special function register Y_START_ADDR, CB_START_ADDR, CR_START_ADDR must be set. 352 Start address location of register 176 176 VLX frame memory size QCIF Y 144 QCIF Cb 72 QCIF Cr 72 VLDed frame memory size = (352x144) + (176x72) + (176x72) = 76032 Bytes Figure 26-.7 External memory amount in VLD mode. 26-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR VLX 1 FRAME IMAGE 32bit 8 0 24 16 1 MB Luminance 40 32 56 48 8 0 24 16 40 32 56 48 8 0 24 16 40 32 56 48 25 17 41 33 57 49 9 1 25 17 41 33 57 49 9 1 25 17 41 33 57 49 9 1 10 2 26 18 42 34 58 50 10 2 26 18 42 34 58 50 10 2 26 18 42 34 58 50 11 3 27 19 43 35 59 51 11 3 27 19 43 35 59 51 11 3 27 19 43 35 59 51 12 4 28 20 44 36 60 52 12 4 28 20 44 36 60 52 12 4 28 20 44 36 60 52 13 5 29 21 45 37 61 53 13 5 29 21 45 37 61 53 13 5 29 21 45 37 61 53 14 6 30 22 46 38 62 54 14 6 30 22 46 38 62 54 14 6 30 22 46 38 62 54 15 7 31 23 47 39 63 55 15 7 31 23 47 39 63 55 15 7 31 23 47 39 63 55 8 0 24 16 40 32 56 48 8 0 24 16 40 32 56 48 8 0 24 16 40 32 56 48 9 1 25 17 41 33 57 49 9 1 25 17 41 33 57 49 9 1 25 17 41 33 57 49 10 2 26 18 42 34 58 50 10 2 26 18 42 34 58 50 10 2 26 18 42 34 58 50 11 3 27 19 43 35 59 51 11 3 27 19 43 35 59 51 11 3 27 19 43 35 59 51 12 4 28 20 44 36 60 52 12 4 28 20 44 36 60 52 12 4 28 20 44 36 60 52 13 5 29 21 45 37 61 53 13 5 29 21 45 37 61 53 13 5 29 21 45 37 61 53 14 6 30 22 46 38 62 54 14 6 30 22 46 38 62 54 14 6 30 22 46 38 62 54 15 7 31 23 47 39 63 55 15 7 31 23 47 39 63 55 15 7 31 23 47 39 63 55 8 0 24 16 40 32 56 48 8 0 24 16 40 32 56 48 9 1 25 17 41 33 57 49 9 1 25 17 41 33 57 49 10 2 26 18 42 34 58 50 10 2 26 18 42 34 58 50 11 3 27 19 43 35 59 51 11 3 27 19 43 35 59 51 12 4 28 20 44 36 60 52 12 4 28 20 44 36 60 52 13 5 29 21 45 37 61 53 13 5 29 21 45 37 61 53 14 6 30 22 46 38 62 54 14 6 30 22 46 38 62 54 15 7 31 23 47 39 63 55 15 7 31 23 47 39 63 55 Figure 26-8 VLD output coefficient format VLD block has 3 major blocks. They are shifter, entropy decoding, run length decoding (RLD), Shifter include entropy coder. The operation and the sequence of the VLD operation are reverse to the VLC. Shifter The shifter gives the coded bit stream to the entropy-decoding block and does the shifting operation requested from the entropy-decoding block. The shifting operation is executed during the decoding process to give the left aligned coded bit stream to the entropy-decoding block. Entropy decoder The entropy-decoding process has two steps. In first step, it extracts one code from the coded bit stream from the shifter and in second, it finds the symbol address corresponding to that code. In general case, during the process to extract one code the address for the symbol is calculated. The output of Entropy decoder are Run, Level, Last value. These value is input of RLD module. 26-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 VLX S3C24A0 RISC MICROPROCESSOR Run length decoder The output of the entropy decoding is (LAST,RUN, LEVEL) in MPEG mode. They are decoded to a sequence of the coefficients. This operation is done in the run-length decoding block. It is the reverse operation of the RLC block. And reads the sequence of coefficients from the run-length decoding block and writes the coefficients to the DCT/Q memory in zigzag address order or DCTQ zigzag address order . This is the reverse operation in VLC RLC. VLD operation. VLD is operated by 1 MB opunit. Decoding start address and bit count are accepted on each MB by S/W processing. 31 8 (SFR : BIT_COUNT ) 16 24 0 31 Figure 26-9 MSB is first bit value in output bit stream VLD output is saved image format in external memory. Figure 26-7, 26-8 show the external memory DC prediction inverse coding and scanning are need in S/W processing in Intra mode. VLD processing explained Figure 26-10 VLD flow chart. VLD flow chart is partitioned S/W processing and H/W processing. 26-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR VLX ON VOP header Dec. get VOP information MB Header Dec. MB mode information VLD SFR set and triggering. CBP information Bit_SADDR, START_BIT_CNT Coefficient VLD operation polling sigal or interrupt signal gen. Get VLD_EADDR END_BIT_CNT MB == OP_UNIT No No Yes Intra Yes INTRA DC/AC inverse prediction and scannig H/W operation No S/W operation Yes DCTQ transter MB == FRAME Yes ON Figure 26-10 VLD flow chart and s/w and h/w processing partition. Start signal and busy signal and interrupt relation is Fig.26-11 HCLK VLX_CPU_START or Write_start ( from DCTQ ) VLX_BUSY VLX_IRQ STATE VLXoperating period by OPUNIT MB Figure 26-11 Start signal, busy signal and interrupt signal in VLD mode. 26-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 VLX S3C24A0 RISC MICROPROCESSOR VLX( VLC and VLD ) SPECIAL REGISTERS VLX common SFR . Register COMMON1 Address 0x4940_0000 R/W R/W Bit [0] [1] [2] [3] [4] [5] [8:6] [20:9] [21] Description VLX common control register 1 Description VLX system on / off control bit, not start bit reserved 1 : Frame START 0 : not frame start 1 : Encoder or Decoder start 0 : disable 1 : Encoder 0 : Decoder 1 : Interrupt mode enable reserved Operation MB count reserved 0 : disable Reset Value 0x0000_0000 Initial State 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x000 0x0 COMMON1 VLX ON FRAME_START VLX_START ENC_MODE INT_ENABLE OP_UNIT_SFR Note 1. 2. VLX _ON bit is on / off control. FRAME START and CPU START must down before next COMMON1 set. Because of these signal is generated one pulse signal in VLX internal module ( only detect rising edge this signal ). 3. 4. 5. FRAME_START signal must be set 1 time per 1 frame. And it must be set 0 before next OP_UNIT processing start. ENC_MODE 1 : VLC operation , 0 : VLD operation. INT_ENABLE 0 : only polling mode ( busy signal is VLX_BUSY value in VLX_OUT1 special function register .) 6. OP_UNIT SFR count value of macro block operation in VLC mode. Interrupt signal generation on end of OP_UNIT. OP_UNIT_SFR must be set 1 value in VLD mode. 7. COMMON[1] and COMMON[8:6] must be set value `0' 8. COMMON[21] must be set value `1'. FRAME START ADDR Register FRAME_START_Y FRAME_START_Y Address 0x4940_0004 Bit R/W R/W Description Y coeff. frame start address Description Reset Value 0x0000_0000 Initial State 26-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR VLX Y img frame start addr Register FRAME_START_CB FRAME_START_CB CB img frame start addr [31:0] Address 0x4940_0008 Bit [31:0] Y coeff. frame start address in VLD mode 0x0000_0000 Reset Value 0x0000_0000 Initial State 0x0000_0000 R/W R/W Description CB coeff. frame start address Description CB coeff. frame start address in VLD mode Register FRAME_START_CR FRAME_START_CR CR img frame start addr Address 0x4940_000c Bit [31:0] R/W R/W Description CR coeff. frame start address Description Reset Value 0x0000_0000 Initial State 0x0000_0000 CR coeff. frame start address in VLD mode VLX CONTROL REGISTER( VLX_CON) Register VLC_CON1 Address 0x4940_0010 Bit [9:0] [10] [12:11] [13] [14] R/W R/W Description Control register in VLC mode Description Image x size set register reserved Scanning method select control bits. reserved S/w reset active high. Reset Value 0x0000_0000 Initial State 0x000 0x0 0x0 0x0 0x0 VLC_CON1 IMG_XSIZE_SFR SEL_SCAN_SFR SW_RESET Note 1.IMG_XSIZE_SFR is pixel count value. Ex ) QCIF = 176, CIF = 352 2. 2'b00 : zigzag scan, 2'b11 : DCTQ zigzag format by dctq module format , others : ordered format. 3. S/W reset active high. And need to be down after high. 4. COMMON[10] must be set value `1' 5. COMMON[13] must be set value `0' 26-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 VLX S3C24A0 RISC MICROPROCESSOR Register VLC_CON2 Address 0x4940_0014 R/W R/W Description Reserved Reset Value - Register VLC_CON3 Address 0x4940_0018 Bit R/W R/W Description VLC bit stream start addr. Description External address saved VLCed output stream. Reset Value 0x0000_0000 Initial State 0x0000_0000 VLC_CON3 VLCED_ADDR [31:0] Note. VLCED ADDR is bit stream base address output in VLC mode. VLCED ADDR[8:0] bit must be set 0 value!!. Register VLC_CON4 Address 0x4940_001c R/W R/W Description reserved Reset Value 0x0000_0000 26-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR VLX VLD CONTROL REGISTER( VLD_CON) Register VLD_CON1 Address 0x4940_0020 R/W R/W Bit [11:0] [17:12] [18] [19] [25:20] [30:26] [31] Description VLD control value setting register Description reserved First bit count value when VLD start 1 : intra, 0 : inter mode in VLD reserved CBP value QP value Reserved Reset Value 0x0000_0000 Initial State 0x00 0x0 0x00 0x00 - VLD_CON1 START_BIT_CNT IS_INTRA_VLD CBP_VLD_SFR QP_SFR Note 1. BIT_STUFF_SFR is bit count number of first start macro block bit streams. 2. Bit[11:0], Bit[19] must be set value `0'. 3. Bit[31] must be set `0x1' Address 0x4940_0024 R/W R/W Bit [31:0] R/W R/W Description VLD BIT_SADDR Description VLD Bit stream start bit in VLD mode. Description Reserved Reset Value 0x0000_0000 Initial State 0x0000_0000 Reset Value - Register VLD_CON2 VLD_CON2 BIT_SADDR Register VLD_CON3 Address 0x4940_0028 26-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 VLX S3C24A0 RISC MICROPROCESSOR VLX OUTPUT REGISTER 1 ( VLX_CON 1 ) - read only Register VLX_OUT1 Address 0x4940_002c R/W R Bit [0] [6:1] Description VLX output information register. 1 Description VLX busy signal Next start bit count Reset Value 0x0000_0000 Initial State 0x0 0x00 VLX_CON1 VLD_BUSY N_ST_BIT_CNT VLX OUTPUT REGISTER 2 ( VLX_CON 2 ) - read only Register VLX_OUT2 Address 0x4940_0030 Bit [31:0] Next start address. R/W R Description VLX output information register. 2 Description Reset Value 0x0000_0000 Initial State 0x0000_0000 VLX_CON2 N_START_ADDR Note 1. N_START_BIT_CNT is next start bit counter number for next MB decoding.. 2. N_START_ADDR is next start address for next MB decoding. 26-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR POST PROCESSOR POST Processor (Preliminary) 1. Overview Post processor performs video/graphic scale, video format conversion and color space conversion. It is composed of Data-Path, DMA controller and Register files as shown in the overall block diagram of Figure 27-1. Overall features are summarized as follows. Register Files InFIFO AHB BUS Y Cb Cr Scale & Format Conversion Line Pre Main Memory Scale Scale Line Main Pre Memory Scale Scale Line Main Pre Memory Scale Scale CSC OutFIFO Color Space Con. RGB DMA Controller Figure 27-1. Block Diagram of Post Processor Overall Features AMBA AHB v2.0 compatible interface Dedicated DMA with offset address 3 Channel scaling pipelines for video/graphic scaling up/down or zooming in/out Video input format: 420, 422 format Graphic input format: 16-bit (565format) or 24-bit 27-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 POST PROCESSOR S3C24A0 RISC MICROPROCESSOR Output format: 16-bit (565 format) / 24-bit graphic data Programmable source and destination image size up to 2048 x 2048 resolution Programmable scaling ratio Format conversion for video signals Color space conversion Separate processing clock with AHB interface clock 27-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR POST PROCESSOR 2. A Source and Destination Image Data Format Various source and destination image formats can be selected according to the mode configuration as described in Table 27-1. Source image format is one of YCbCr420, YCbCr422, RGB16-bit (565format) and RGB 24-bit format. Destination image format is either RGB 16-bit (565format) or RGB 24-bit. In the case of YCbCr420 source image format, each component of Y, Cb and Cr is stored in each own separated address space without any interleaving as shown in Case A of Figure 27-2 (a) and Figure 27-3. In the other cases, either byte or half-word interleaving is applied within unified address space as shown in Figure 27-2 (b). Byte interleaving order of YCbCr422 source image is selectable either YCbYCr or CbYCrY as shown in case B and C of Figure 27-2 (b) and Figure 27-3. Byte order of RGB 24-bit and half-word order of RGB 16-bit are shown in case D and E of Figure 27-2 (b) and Figure 27-3. In both cases of YCbCr420 and YCbCr422 source image format, whether MPEG4 format or MPEG2/H.263 format needs to be selected according to the sampling position of the chroma information as shown in Figure 27-4. All source and destination image data need to be stored in memory system aligned with word boundary. It means that neither byte nor half-word size DMA operations are supported (see chapter 27-4 for DMA operation). Therefore, the width of source and destination image should be selected to satisfy the word boundary condition (see chapter 27-3 for image size). Table 27-1. Mode configuration for video/graphic source format and the corresponding data format MODE[8] SRC420 MODE[3] InRGB MODE[2] INTERLEAVE MODE[1] InRGB Format MODE[0] InYCbCr Format Description Video/Graphic Format 420 YCbCr Format 422 YCbYCr Format 422 CbYCrY Format RGB 24-bit true color RGB 16-bit Format Data Format in Fig27-2 and 3 1 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 x 0 1 x x A B C D E 27-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 POST PROCESSOR S3C24A0 RISC MICROPROCESSOR WORD WORD MSB LSB YY Cb Cb Cr Cr Video Data MSB Y Cb Cb Y LSB Y Cr Cr Y B C Y 1 Frame Cb Cr YY Cb Cb Cr Cr A 1 Frame Or Graphic Data x R G B D E PixelN+1 PixelN Memory Space (a) Non-Interleaving Memory Space (b) Interleaving Figure 27-2 Data format stored in external memory 31 Case A Case B Case C Case D 24 23 16 15 87 0 Y/Cb/Cr N Cr N YN BN Y/Cb/Cr N+3 Y/Cb/Cr N+2 Y/Cb/Cr N+1 Y N+1 Cb N Don't Care Cb N Y N+1 RN 21 20 B[4:0] 16 15 R[4:0] YN Cr N GN 31 Case E R[4:0] 27 26 G[5:0] 11 10 G[5:0] 54 B[4:0] 0 Pixel N+1 Figure 27-3 Byte and half-word organization Pixel N 27-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR POST PROCESSOR 1/2dx 1/2dx 1/4dx dx 1/2dx 1/2dx dx 1/4dy 1/2dy 1/2dy 1/2dy 1/2dy 1/4dy dy dy (a) YCbCr420 (MPEG2/H.263) (b) YCbCr420 (MPEG4) 1/2dx 1/2dx 1/4dx dx 1/2dx 1/2dx dx 1/4dy 1/2dy 1/2dy 1/2dy 1/2dy 1/4dy dy dy (c) YCbCr422 (MPEG2/H.263) (d) YCbCr422 (MPEG4) Figure 27-4 Sampling position of YCbCr420 and YCbCr422 format (x: Luma sample and : Chroma sample) 27-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 POST PROCESSOR S3C24A0 RISC MICROPROCESSOR 3. Image Size and Scale Ratio The RGB graphic source image size is determined by number of pixels along to horizontal and vertical directions. YCbCr420 and YCbCr422 source image size is determined only by numbers of Y samples along to horizontal and vertical directions. Destination image size is determined by dimension of final RGB graphic image, after color space conversion if source image is YCbCr image. As explained in the previous section, SRC_Width and DST_Width satisfy the word boundary constraints such that the number of horizontal pixel can be represented to kn where n = 1,2,3, ... and k = 1 / 2 / 8 for 24bppRGB / 16bppRGB / YCbCr420 image, respectively. DST_Width SRC_Width SRC_Height DST_Height Source Image Destination Image Figure 27-5 Source destination image size The other control registers of pre-scaled image size, pre-scale ratio, pre-scale shift ratio and main scale ratio are defined according to the following equations. If ( SRC_Width >= 64 x DST_Width ) { Exit(-1); /* Out Of Horizontal Scale Range */ } else if (SRC_Width >= 32 x DST_Width) { PreScale_H_Ratio = 32; else if (SRC_Width >= 16 x DST_Width) { PreScale_H_Ratio = 16; else if (SRC_Width >= 8 x DST_Width) { PreScale_H_Ratio = 8; else if (SRC_Width >= 4 x DST_Width) { PreScale_H_Ratio = 4; else if (SRC_Width >= 2 x DST_Width) { PreScale_H_Ratio = 2; else { PreScale_H_Ratio = 1; H_Shift = 0; } H_Shift = 5; } H_Shift = 4; } H_Shift = 3; } H_Shift = 2; } H_Shift = 1; } PreScale_DSTWidth = SRC_Width / PreScale_H_Ratio; dx = ( SRC_Width << 8 ) / ( DST_Width << H_Shift); 27-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR POST PROCESSOR If ( SRC_Height >= 64 x DST_Height ) { Exit(-1); /* Out Of Vertical Scale Range */ } else if (SRC_Height >= 32 x DST_Height) { PreScale_V_Ratio = 32; else if (SRC_Height >= 16 x DST_Height) { PreScale_V_Ratio = 16; else if (SRC_Height >= 8 x DST_Height) { PreScale_V_Ratio = 8; else if (SRC_Height >= 4 x DST_Height) { PreScale_V_Ratio = 4; else if (SRC_Height >= 2 x DST_Height) { PreScale_V_Ratio = 2; else { PreScale_V_Ratio = 1; V_Shift = 0; } PreScale_DSTHeight = SRC_Height / PreScale_V_Ratio; dy = ( SRC_Height << 8 ) / ( DST_Height << V_Shift); V_Shift = 5; } V_Shift = 4; } V_Shift = 3; } V_Shift = 2; } V_Shift = 1; } PreScale_SHFactor = 10 - ( H_Shit + V_Shift); 27-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 POST PROCESSOR S3C24A0 RISC MICROPROCESSOR 4. DMA operation of Source and Destination Image There are three address categories such as start address, end address and offset address for DMA operation. Each address category consists of three source address components of Y/Cb/Cr and one destination address component of RGB. If a source image is stored by the non-interleaved format such as YCbCr420, all source address components are valid as shown in Figure 27-6 (a). If a source image is stored by the interleaved format such as a RGB graphic format or an YCbCr422 format, only Y component of three source components is valid and two chroma address components are invalid as shown in Figure 27-6 (b). The details of start and end address are define as follows. ADDRStart_Y ADDREnd_Y ADDRStart_Cb ADDREnd_Cb ADDRStart_Cr ADDREnd_Cr Y Source Image Video Data Or Graphic Data ADDRStart_Y ADDREnd_Y Cb Cr ADDRStart_RGB ADDREnd_RGB RGB Destination Image RGB ADDRStart_RGB ADDREnd_RGB (a) Non-Interleaving (b) Interleaving Figure 27-6 Start and end address set according to memory allocation type 27-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR POST PROCESSOR Start address Start address of ADDRStart_Y/Cb/Cr/RGB points the first word address where the corresponding component of Y/Cb/Cr/RGB is read or written. Each one should be aligned with word boundary (i.e. ADDRStart_X[1:0] = 00). ADDRStart_Cb and ADDRStart_Cr are valid only for the YCbCr420 source image format. End address ADDREnd_Y = ADDRStart_Y + Memory size for the component of Y = ADDRStart_Y + (SRC_Width x SRC_Height) x ByteSize_Per_Pixel + Offset_Y x (SRC_Height-1) ADDREnd_Cb (Valid for YCbCr420 source format) = ADDRStart_Cb + Memory size for the component of Cb = ADDRStart_Cb + (SRC_Width/2 x SRC_Height/2) x ByteSize_Per_Pixel + Offset_Cb x (SRC_Height/2-1) ADDREnd_ Cr (Valid for YCbCr420 source format) = ADDRStart_ Cr + Memory size for the component of Cr = ADDRStart_Cr + (SRC_Width/2 x SRC_Height/2) x ByteSize_Per_Pixel + Offset_Cr x (SRC_Height/2-1) ADDREnd_RGB = ADDRStart_RGB + Memory size for the component of RGB data = ADDRStart_RGB + (DST_Width x DST_Height) x ByteSize_Per_Pixel + Offset_RGB x (DST_Height-1) Where, Offset_Y/Cb/Cr/RGB = Memory size for offset per a horizontal line = Number of pixel (or sample) in horizontal offset x ByteSize_Per_Pixel (or Sample) ByteSize_Per_Pixel = 1 for YCbCr420 2 for 16-bit RGB and YCbCr422 4 for 24-bit RGB 27-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 POST PROCESSOR S3C24A0 RISC MICROPROCESSOR Offset is used for the following two situations. One is to fetch some parts of source image in order to zoom in/out as shown in Figure 27-7 (a). The other is to restore destination image for PIP (picture-in-picture) applications as shown in Figure 27-7 (b). Of course, the word boundary constraints should be satisfied in both cases. Dst_Width Original Image Src_Width Dst_Height Src_Height Source Image Offset Destination Image (Zoom In/Out) a) Zoom In/Out Background Image Src_Width Dst_Width Src_Height Offset b) PIP Dst_Height Source Image Destination Image(PIP) Figure 27-7 Offset for (a) source image for zoom in/out operation and (b) destination image for PIP applications 5. Starting and Terminating of POST Processor Starting and terminating the operation of POST-Processor are controlled by two control register such as POSTENVID and POSTINT as shown in Figure 27-8. "POSTENVID" triggers the operation of POST PROCESSOR. It is automatically de-asserted when all operations of the given frame are completed. Before asserting "POSTENVID", all control registers should be set to the proper value as explained in the previous chapters. When all operations are completed, interrupt pending register is asserted (POSTINT=1), if interrupt enable signal is asserted (INTEN=1). The POSTINT signal, directing to the interrupt controller, should be cleared by the interrupt service routine. Otherwise, polling POSTENVID is used to detect the end of the operation. 27-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR POST PROCESSOR Users set Automatic clear/assertion User clear if asserted (Start operation) (Terminate operation) POSTENVID Control Register Set (INTEN=1) (INTEN=0) POSTINT Figure 27-8 Start and termination of the operation of POST PROCESSOR 6. Register File Lists MODE Control Register Register MODE Address 0X4A100000 R/W R/W Description Mode Register [9:0] Reset Value 0xB12 MODE Reserved Reserved MPEG4 Bit 11 10 [9] This bit should be `1'. This bit should be `0'. Description Initial State 1 0 1 Sampling position of chroma information. 0 for H.263/MPEG2 and 1 for MPEG4. It is valid only for YCbCr source image (i.e. InRGB = 0) 0 for YCbCr422 and 1 for YCbCr420 source format. It is valid only for YCbCr source image (i.e. InRGB = 0) Interrupt Enable. It determines whether the POSTINT signal is asserted or not, when the processing of the current frame is finished. 0: disable, 1 : enable. Interrupt Pending Bit. If INTEN is enabled, it is automatically asserted right after finishing operation of the current frame. It should be cleared by interrupt service routine. 0 : disable, 1 : enable. Enable Video Processing. It turns on the operation of PostProcessor. It is de-asserted automatically after operation of the current frame is finished. It should be disabled (POSTENVID=0) during control SRC420 [8] 1 0 INTEN [7] POSTINT [6] 0 POSTENVID [5] 0 27-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 POST PROCESSOR S3C24A0 RISC MICROPROCESSOR register configuration state. OutRGBFormat [4] It determines the output format of destination image. 0 for 16-bit (565 format) RGB and 1 for 24-bit RGB. It indicates the input color space of source image. 0 for YCbCr or 1 for RGB. It indicates the data format of YCbCr. 0 for Non-Interleaved format (Each component of Y, Cb and Cr is access by the word). 1 for Interleaved format (All components of Y, Cb and Cr are mixed inside single word). It should be 1 when source image is RGB data (or InRGB =1). If the source image is in RGB color space (or InRGB=1), it indicates InRGBFormat [1] the data format of graphic image. 0 for 16-bit (565 format) and 1 for 24-bit. Otherwise (or InRGB=0), it should be remains to 1. It determines the byte organization of word data when the source InYCbCrFormat [0] image is interleaved YCbCr format (InRGB=0 and INTERLEAVE=1). 0 for YCbYCr(type B in Fig. 27-2(b)) and 1 for CbYCrY (type C in Fig.27-2(b) . 0 1 InRGB [3] 0 0 INTERLEAVE [2] 1 Pre-Scale Ratio Register Register PreScale_Ratio Address 0X4A100004 R/W R/W Description Pre-Scale ratio for vertical and horizontal. Reset Value 0x0 PreScale_Ratio PreScale_V_Ratio PreScale_H_Ratio Bit [13:7] [6:0] Description Pre-scale ratio along to vertical direction (see chapter 27-3) Pre-scale ratio along to horizontal direction (see chapter 27-3) Initial State 0x0 0x0 Pre-Scale Image Size Register Register PreScaleImgSize Address 0X4A100008 R/W R/W Description Pre-Scaled image size Reset Value 0x0 27-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR POST PROCESSOR PreScaleImgSize PreScale_DSTHeight PreScale_DSTWidth Bit [23:12] [11:0] Description Pre-Scaled image height (see chapter 27-3) Pre-Scaled image width (see chapter 27-3) Initial State 0x0 0x0 Source Image Size Register Register SRCImgSize Address 0X4A10000C R/W R/W Description Source image size Reset Value 0x0 SRCImgSize SRCHeight SRCWidth Bit [23:12] [11:0] Description Source image height (see chapter 27-3) Source image width (see chapter 27-3) Initial State 0x0 0x0 Horizontal Main Scale Ratio Register Register MainScale_H_Ratio Address 0X4A100010 R/W R/W Description Main scale ratio along to horizontal direction Reset Value 0x0 MainScale_H_Ratio MainScale_H_Ratio Bit [8:0] Description Main scale ratio along to horizontal direction (see chapter 27-3) Initial State 0x0 Vertical Main Scale Ratio Register Register MainScale_V_Ratio Address 0X4A100014 R/W R/W Description Main scale ratio along to vertical direction Reset Value 0x0 MainScale_V_Ratio Bit Description Initial State 27-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 POST PROCESSOR S3C24A0 RISC MICROPROCESSOR MainScale_V_Ratio [8:0] Main scale ratio along to vertical direction (see chapter 27-3) 0x0 Destination Image Size Register Register DSTImgSize Address 0X4A100018 R/W R/W Description Destination image size Reset Value 0x0 SRCImgSize DSTHeight DSTWidth Bit [23:12] [11:0] Description Destination image height (see chapter 27-3) Destination image width (see chapter 27-3) Initial State 0x0 0x0 Pre-Scale Shift Factor Register Register PreScale_SHFactor Address 0X4A10001C R/W R/W Description Pre-scale shift factor Reset Value 0x0 SRC_Width PreScale_SHFactor Bit [3:0] Description Pre-scale shift factor (see chapter 27-3) Initial State 0x0 DMA Start Address Register Register ADDRStart_Y Address 0X4A100020 R/W R/W Bit [30:0] Description DMA Start address for Y or RGB component of source image Reset Value 0x2000_0000 Register ADDRStart_Cb Address 0X4A100024 R/W R/W Bit [30:0] Description DMA Start address for Cb component of source image Reset Value 0x2000_0000 27-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR POST PROCESSOR Register ADDRStart_Cr Address 0X4A100028 R/W R/W Bit [30:0] Description DMA Start address for Cr component of source image Reset Value 0x2000_0000 Register ADDRStart_RGB Address 0X4A10002C R/W R/W Bit [30:0] DMA Description Start address for RGB Reset Value 0x2000_0000 component of destination image DMA End Address Register Register Address R/W Bit Description DMA End address for Y or RGB ADDREnd_Y 0X4A100030 R/W [30:0] component of source image (see chapter 27-4) 0x2000_62fc Reset Value Register ADDREnd_Cb Address 0X4A100034 R/W R/W Bit [30:0] Description DMA End address for Cb component of source image (see chapter 27-4) Reset Value 0x2000_62fc Register ADDREnd_Cr Address 0X4A100038 R/W R/W Bit [30:0] Description DMA End address for Cr component of source image (see chapter 27-4) Reset Value 0x2000_62fc Register Address R/W Bit Description DMA End address for RGB component Reset Value ADDREnd_RGB 0X4A10003C R/W [30:0] of destination image (see chapter 274) 0x2000_62fc Offset Register Register Address R/W Bit Description Reset Value 27-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 POST PROCESSOR S3C24A0 RISC MICROPROCESSOR Offset_Y 0X4A100040 R/W [23:0] Offset of Y component for fetching source image (see chapter 27-4) 0 Register Offset_Cb Address 0X4A100044 R/W R/W Bit [23:0] Description Offset of Cb component for fetching source image (see chapter 27-4) Reset Value 0 Register Offset_Cr Address 0X4A100048 R/W R/W Bit [23:0] Description Offset of Cr component for fetching source image (see chapter 27-4) Reset Value 0 Register Offset_RGB Address 0X4A10004C R/W R/W Bit [23:0] Description Offset of RGB component for restoring destination image (see chapter 27-4) Reset Value 0 27-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER LCD CONTROLLER (PRELIMINARY) OVERVIEW The LCD controller within S3C24A0 consists of logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver. The LCD controller supports 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, 8-bit per pixel for interfacing with the palettized TFT color LCD panel, 8-bit, 16-bit per pixel and 18-bit per pixel non-palettized color display. The LCD controller can be programmed to support the different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate. FEATURES Video Clock Source External Panel Interface HCLK Supports up to 18 bit RGB I/F Panel(RGB Parallel mode) Supports 6 bit RGB I/F Panel(RGB Serial mode) Supports both RGB and BGR mode OSD(Overlay) Supports 8 BPP (bit per pixel) palettized or non-palettized color displays for TFT Supports 16 and 18 BPP non-palettized color displays for color TFT Supports X,Y indexed position Supports 8 bit Alpha blending : per Plan or per Pixel(18 BPP only) Support 18 bit Color Key function Color Level of TFT Display Size Configurable Burst Length Dual Palette Soft Scrolling Virtual Screen Double Buffering Dithering Supports 1, 2, 4 and 8 BPP(bit per pixel) palettized color displays for TFT Supports 8, 16 and 18 BPP non-palettized color displays for TFT Supports 640x480, 320x240, 176x192 and others Support programmable 4 / 8 / 16 Burst DMA operation 256 x 24 bit palette (2ea for each Background and Foreground image) Horizontal : 1 Byte resloution Vertical : 1 pixel resolution Virtual image can has up to 16MB image size. Frame buffer alternating by one control bit Patented 4x4 dither matrix implemetation 28-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR EXTERNAL INTERFACE SIGNAL Name XvVCLK XvHSYNC XvVSYNC XvVDEN XvVD[17:12] Type Output Output Output Output Output Source/Destination Pad Pad Pad Pad Pad Description Video Clock Signal Horizontal Sync. Signal Vertical Sync. Signal Video Data Enable/Valid LCD pixel data output for Red in RGB Parallel Mode LCD pixel data output in RGB Serial Mode XvVD[11:6] XvVD[5:0] Output Output Pad Pad LCD pixel data output for Green in RGB Parallel Mode LCD pixel data output for Blue in RGB Parallel Mode 28-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER BLOCK DIAGRAM REGBANK TIMEGEN XvVCLK XvHSYNC XvVSYNC XvVDEN HCLK VIDCLKGEN LCDCDMA VIDPRCS XvVD[17:0] Figure 28-1. LCD Controller Block Diagram The LCD controller within S3C24A0 is used to transfer the video data and to generate the necessary control signals such as, XvVSYNC, XvHSYNC, XvVCLK, and XvVDEN. As well as the control signals, S3C24A0 has the data ports for video data, which are XvVD[17:0] as shown in Figure 28-1. The LCD controller consists of a REGBANK, LCDCDMA, VIDPRCS, TIMEGEN, and VIDCLKGEN (See Figure 28-1 LCD Controller Block Diagram). The REGBANK has 26 programmable register sets and 256x24 palette memory which are used to configure the LCD controller. The LCDCDMA is a dedicated DMA, which it can transfer the video data in frame memory to LCD driver, automatically. By using this special DMA, the video data can be displayed on the screen without CPU intervention. The VIDPRCS receives the video data from LCDCDMA and sends the video data through the VD[17:0] data ports to the LCD driver after changing them into a suitable data format, for example 8bit per pixel mode(8 BPP Mode) or 16-bit per pixel mode(16 BPP Mode). The TIMEGEN consists of programmable logic to support the variable requirement of interface timing and rates commonly found in different LCD drivers. The TIMEGEN block generates , XvVSYNC, XvHSYNC, XvVCLK, and XvVDEN. The description of data flow is as follows: FIFO memory is present in the LCDCDMA. When FIFO is empty or partially empty, LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode(Consecutive memory fetching of 4 / 8 / 16 words per one burst request without allowing the bus mastership to another bus master during the bus transfer). When this kind of transfer request is accepted by bus arbitrator in the memory controller, there will be 4 /8 /16 successive word data transfers from system memory to internal FIFO. The total sizes of FIFO are 128x2 words, which consist of 128 words for background FIFO and 128 words foreground FIFO, respectively. The S3C24A0 has two FIFOs because it needs to support the OSD display mode. In case of one screen display mode, the background FIFO could only be used. LCD controller supports overlay function which enables overlaying any image (OSD, foreground image) which is small or same size can be blended with background image with programmable alpha blending or color (chroma) key function. 28-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR TIMING CONTROLLER OPERATION The TIMEGEN generates the control signals for LCD driver such as, , XvVSYNC, XvHSYNC, XvVCLK, and XvVDEN signal. These control signals are highly related with the configuration on the LCDTCON1/2/3 registers in the REGBANK. Base on these programmable configurations on the LCD control registers in REGBANK, the TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD drivers. The VSYNC signal is asserted to cause the LCD's line pointer to start over at the top of the display. The generation of VSYNC and HSYNC pulse is controlled by the configuration of both the HOZVAL field and the LINEVAL field in the LCDTCON3 register. The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to the following equations: HOZVAL = (Horizontal display size) -1 LINEVAL = (Vertical display size) -1 0 MUX HCLK Divider 1/[(CLKVAL+1)x2] VCLK 1 CLKDIR Figure 28-2. Clock Selection The rate of VCLK signal can be controlled by the CLKVAL field in the LCDCON1 register. The table below defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 0. XvVCLK (Hz) =HCLK/ [(CLKVAL+1) x2] The frame rate is VSYNC signal frequency. The frame rate is related with the field of VSYNC, VBPD, VFPD, LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, CLKVAL registers. Most LCD driver needs their own adequate frame rate. The frame rate is calculated as follows; Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( Frequency of Clock source ) } ] Table 28-1. Relation between XvVCLK and CLKVAL (TFT, Freq. of Video Clock Source=60MHz) CLKVAL 1 2 60MHz/X 60 MHz/4 60 MHz/6 XvVCLK 15.0 MHz 10.0 MHz 28-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER : 63 : 60 MHz/128 : 492 kHz 28-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR VIDEO OPERATION The TFT LCD controller within S3C24A0 supports 1, 2, 4 or 8 BPP(bit per pixel) palettized color displays and 8, 16 non-palettized high-color or 18 BPP non-palettized true-color displays. The TFT LCD controller also supports On-Screen Display with 256-level alpha blending and color (chroma) key functions. The background image and foreground image (OSD image) should have a frame buffer of each image. OSD (ON-SCREEN DISPLAY) : OVERLAY OSD (On Screen Display) and blending operation as shown in Fig 28-3 are established for video overlay or other graphics applications. Two blending schemes are provided according to the control bit of OSD_BLD_PIX. One is per-pixel blending for 18 BPP mode display (OSD_BLD_PIX = 1) and the other is per-plane bending for 8/16/18 BPP mode display (OSD_BLD_PIX = 0). LCDB1ADDR1/2/3, LCDB2ADDR1/2/3 registers are defined to perform DMA for OSD image. Four screen coordinates such as OSD_LEFT_TOP_X, OSD_LEFT_TOP_Y, OSD_RIGHT_BOT_X and OSD_RIGHT_BOT_Y determines where the OSD image is located on the whole background image. The level of blending is controller by OSD_ALPHA as following manner. (OSD_LEFTTOP_X, OSD_LEFTTOP_Y) Background Frame Buffer (OSD_RIGHTBOT_X, OSD_RIGHTBOT_Y) LCD Controller Foreground Frame Buffer(OSD) System Memory (a) Memory allocation (b) Blending Fig 28-3 OSD Procedure 28-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER COLOR-KEY FUNCTION The S3C24A0 can support color-key function for the various effect of image mapping. Color image, which is specified by COLOR-KEY register, of OSD layer will be substituted by background image for special functionality, as cursor image or pre-view image of the camera. Foreground Image Background Image Blending Color Key Fig 28-4 Blending and Color Key function of OSD 28-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR DUAL BUFFER The S3C24A0 LCD controller supports easy and fast way for the dual buffering of frame image. User can take two frame image buffer and select one for active frame buffer using the BDBCON (Background double buffer control) and FDBCON (Foreground double buffer control) register. Pre-defined address sets of frame buffer 1 and frame buffer2 are described at Frame Buffer Register 1,2,3. So, user can select which buffer will be activated by setting of the BDBCON and FDBCON register. Maybe, some applications should need simple changing method of frame buffer namely "ping-pong display" . Pre-view image of camera interface will be good example of dual buffering method. One frame should be used as a display buffer, and the other frame as a updating buffer by camera interface module. 28-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER Memory Data Format (TFT) The LCD controller requests the specified memory format of frame buffer. The next table shows some examples of each display mode. 18 BPP Display [BSWP = 0, HWSWP = 0] D[31:24] 000H 004H 008H Alpha1 Alpha2 Alpha3 D[23:0] P1 P2 P3 ... Note: D[31:24] are used to be the alpha value according to each pixel data when blending mode is per-pixel at 18 BPP. So, user must write appropriate value to this filed. P1 P2 P3 P4 P5 ...... LCD Panel [Memory Storing Order at 18 BPP] D[23:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Data R5 R4 R3 R2 R1 R0 x x G5 G4 G3 G2 G1 G0 x: Don't care, We recommend that those bits are filled with `0'. [XvVD Pin Connection at 18 BPP/Parallel Mode] XvVD Data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 x 8 x 7 6 5 4 3 2 1 x 0 x B5 B4 B3 B2 B1 B0 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 [XvVD Pin Connection at 18 BPP/Serial Mode] XvVD 1 Data 2 Data 3 Data rd nd st 17 16 15 14 13 12 11 - 0 NC NC NC R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 28-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR 16BPP Display [BSWP = 0, HWSWP = 0] D[31:16] 000H 004H 008H ... P1 P3 P5 D[15:0] P2 P4 P6 [BSWP = 0, HWSWP = 1] D[31:16] 000H 004H 008H ... P2 P4 P6 D[15:0] P1 P3 P5 P1 P2 P3 P4 P5 ...... LCD Panel [Memory Storing Method at 16 BPP] (5:6:5) D[15:0] Data (5:5:5:I) D[15:0] Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 [XvVD Pin Connection at 16 BPP/Parallel Mode] (5:6:5) XvVD Data 17 16 15 14 13 12 N C 11 10 9 8 7 6 5 4 B3 3 B2 2 B1 1 B0 0 N C R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 28-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER (5:5:5:I) XvVD 17 16 15 14 13 12 11 10 9 8 7 6 I 5 B4 4 B3 3 B2 2 B1 1 B0 0 I Data R4 R3 R2 R1 R0 I G4 G3 G2 G1 G0 [XvVD Pin Connection at 16 BPP/Serial Mode] (5:6:5) XvVD 1 Data 2 Data 3 Data rd nd st (5:5:5:I) 17 R4 G5 B4 16 R3 G4 B3 15 R2 G3 B2 14 R1 G2 B1 13 R0 G1 B0 12 NC G0 NC 11 - 0 NC NC NC st XvVD 1 Data 2 nd rd 17 R4 G4 B4 16 R3 G3 B3 15 R2 G2 B2 14 R1 G1 B1 13 R0 G0 B0 12 I I I 11 - 0 NC NC NC Data 3 Data 8BPP Display [BSWP = 0, HWSWP = 0] D[31:24] D[23:16] 000H 004H 008H ... P1 P5 P9 P2 P6 P10 D[15:8] P3 P7 P11 D[7:0] P4 P8 P12 [BSWP = 1, HWSWP = 0] D[31:24] D[23:16] 000H 004H 008H ... [Memory Storing Method at Non-palettized 8 BPP] D[7:0] Data 7 6 5 4 3 2 1 0 P4 P8 P12 P3 P7 P11 D[15:8] P2 P6 P10 D[7:0] P1 P5 P9 R2 R1 R0 G2 G1 G0 B1 B0 [XvVD Pin Connection at Non-palettized 8BPP/Parallel Mode] XvVD Data 17 16 15 14 13 12 11 10 9 8 7 N C 6 N C 5 B1 4 B0 3 N C 2 N C 1 N C 0 N C N N N G2 G1 G0 N C C C C [XvVD Pin Connection at Non-palettized 8BPP/Serial Mode] XvVD 1 Data st R2 R1 R0 17 16 15 14 N C 13 N C 12 N C 11 - 0 NC R2 R1 R0 28-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR 2nd Data 3rd Data G2 G1 G0 B1 B0 N C N C N C N C N C N C N C NC NC 28-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER 4BPP Display [BSWP = 0, HWSWP = 0] D[31:28] 000H 004H 008H ... P1 P9 P17 D[27:24] P2 P10 P18 D[23:20] P3 P11 P19 D[19:16] P4 P12 P20 D[15:12] P5 P13 P21 D[11:8] P6 P14 P22 D[7:4] P7 P15 P23 D[3:0] P8 P16 P24 [BSWP = 1, HWSWP = 0] D[31:28] 000H 004H 008H ... P7 P15 P23 D[27:24] P8 P16 P24 D[23:20] P5 P13 P21 D[19:16] P6 P14 P22 D[15:12] P3 P11 P19 D[11:8] P4 P12 P20 D[7:4] P1 P9 P17 D[3:0] P2 P10 P18 2BPP Display [BSWP = 0, HWSWP = 0] D 000H 004H 008H ... [31:30] P1 P17 P33 [29:28] P2 P18 P34 [27:26] P3 P19 P35 [25:24] P4 P20 P36 [23:22] P5 P21 P37 [21:20] P6 P22 P38 [19:18] P7 P23 P39 [17:16] P8 P24 P40 D 000H 004H 008H ... [15:14] P9 P25 P41 [13:12] P10 P26 P42 [11:10] P11 P27 P43 [9:8] P12 P28 P44 [7:6] P13 P29 P45 [5:4] P14 P30 P46 [3:2] P15 P31 P47 [1:0] P16 P32 P48 28-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR 256 PALETTE USAGE (TFT) Palette Configuration and Format Control The S3C24A0 can support the 256 colors palette for various selection of color mapping. The user can select 256 colors from the 24-bit palette data through these three formats. 256 color palette consist of the 256(depth) x 24-bit SPSRAM. Palette supports 6:6:6, 5:6:5(R:G:B), and 5:5:5:1(R:G:B:I) format. When the user use 5:5:5:1 format, the intensity data(I) is used as a common LSB bit of each RGB data. So, 5:5:5:1 format is same as (5+I):G(5+I):B(5+I) format. For example of 5:5:5:1 format, write palette like Table 28-4 and then connect VD pin to TFT LCD panel(R(5+I)=VD[17:13]+VD[12], VD[6] or VD[0], G(5+I)=VD[11:7]+ VD[12], VD[6] or VD[0], B(5+I)=VD[5:1]+ VD[12], VD[6] or VD[0].) At the last, Set PALFRM register to 0x3. Table 28-2. 6:6:6 Palette Data Format INDEX\Bit Pos. 00H 01H ....... FFH Number of VD 23-18 17 R5 R5 ... R5 17 16 R4 R4 ... R4 16 15 R3 R3 ... R3 15 14 R2 R2 ... R2 14 13 R1 R1 ... R1 13 12 R0 R0 ... R0 12 11 G5 G5 ... G5 11 10 G4 G4 ... G4 10 9 G3 G3 ... G3 9 8 G2 G2 ... G2 8 7 G1 G1 ... G1 7 6 G0 G0 ... G0 6 5 B5 B5 ... B5 5 4 B4 B4 ... B4 4 3 B3 B3 ... B3 3 2 B2 B2 ... B2 2 1 B1 B1 ... B1 1 0 B0 B0 ... B0 0 Table 28-3. 5:6:5 Palette Data Format INDEX\Bit Pos. 00H 01H ....... FFH Number of VD 23-16 15 R4 R4 ... R4 17 14 R3 R3 ... R3 16 13 R2 R2 ... R2 15 12 R1 R1 ... R1 14 11 R0 R0 ... R0 13 10 G5 G5 ... G5 11 9 G4 G4 ... G4 10 8 G3 G3 ... G3 9 7 G2 G2 ... G2 8 6 G1 G1 ... G1 7 5 G0 G0 ... G0 6 4 B4 B4 ... B4 5 3 B3 B3 ... B3 4 2 B2 B2 ... B2 3 1 B1 B1 ... B1 2 0 B0 B0 ... B0 1 Table 28-4. 5:5:5:1 Palette Data Format INDEX\Bit Pos. 00H 01H ....... FFH Number of VD 23-16 15 R4 R4 ... R4 17 14 R3 R3 ... R3 16 13 R2 R2 ... R2 15 12 R1 R1 ... R1 14 11 R0 R0 ... R0 13 10 G4 G4 ... G4 11 9 G3 G3 ... G3 10 8 G2 G2 ... G2 9 7 G1 G1 ... G1 8 6 G0 G0 ... G0 7 5 B4 B4 ... B4 5 4 B3 B3 ... B3 4 3 B2 B2 ... B2 3 2 B1 B1 ... B1 2 1 B0 B0 ... B0 1 0 I I ... I 1) NOTES: 1. VD12, VD6 and VD0 has same output value, I. 2. DATA[31:24] is invalid. Palette Read/Write It is prohibited to access Palette memory during the ACTIVE status of the VSTATUS (vertical status) of LCDCON2 register. When the user going to do Read/Write operation on the palette, VSTATUS must be checked. 28-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 I 1 2 3 4 5 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 A[6] B4 B3 B2 B1 B0 I A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel 16BPP 5:5:5+1 Format(Non-Palette) A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 1 2 3 4 5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 A[15] A[14] A[13] A[12]A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel 16BPP 5:6:5 Format(Non-Palette) Figure 28-5. 16BPP Display Types 28-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR INT_FrSyn VSYNC HSYNC VDEN VBPD+1 VSPW+1 LINEVAL +1 1 Frame VFPD+1 1 Line HSYNC VCLK VD[17:0] (Parallel Mode) VD[17:12] (Serial Mode) R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R ... B R G B VDEN HBPD+1 HSPW+1 VFPD+1 HOZVAL+1 Figure 28-6. TFT LCD Timing Example 28-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER VIRTUAL DISPLAY The S3C24A0 supports hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL registers need to be changed(refer to Figure 28-7) but not the values of PAGEWIDTH and OFFSIZE. The size of video buffer in which the image is stored should be larger than LCD panel screen size. OFFSIZE PAGEWIDTH OFFSIZE This is the data of line 1 of virtual screen. This is the data of line 1 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 11 of virtual screen. This is the data of line 11 of virtual screen. LCDBASEU View Port (The same size of LCD panel.) LINEVAL + 1 LCDBASEL This is the data of line 1 of virtual screen. This is the data of line 1 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 11 of virtual screen. This is the data of line 11 of virtual screen. Figure 28-7. Example of Scrolling in Virtual Display Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. . . . . . . Before Scrolling After Scrolling 28-17 BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR REGISTER DESCRIPTION MEMORY MAP Table 28-5. Configuration registers Register LCDCON1 LCDCON2 LCDTCON1 LCDTCON2 LCDTCON3 LCDOSD1 LCDOSD2 LCDOSD3 LCDSADDRB1 LCDSADDRB2 LCDSADDRF1 LCDSADDRF2 LCDEADDRB1 LCDEADDRB2 LCDEADDRF1 LCDEADDRF2 LCDVSCRB1 LCDVSCRB2 LCDVSCRF1 LCDVSCRF2 LCDINTCON LCDKEYCON LCDKEYVAL LCDBGCON LCDFGCON LCDDITHCON Address 0X4A000000 0X4A000004 0X4A000008 0X4A000010 0X4A000014 0X4A000018 0X4A000020 0X4A000024 0X4A000028 0X4A000030 0X4A000034 0X4A000038 0X4A000040 0X4A000044 0X4A000048 0X4A000050 0X4A000054 0X4A000058 0x4A00005C 0x4A000060 0X4A000064 R/W R/W LCD Control 1 R/W LCD Control 2 R/W LCD Time Control 1 R/W LCD Time Control 3 R/W LCD OSD Control Register R/W Foreground image(OSD Image) Left top position set R/W Frame Buffer Start Address 1(Background buffer 1) R/W Frame Buffer Start Address 2(Background buffer 2) R/W Frame Buffer Start Address 1(Foreground buffer 1) R/W Frame Buffer End Address 1(Background buffer 1) R/W Frame Buffer End Address 2(Background buffer 2) R/W Frame Buffer End Address 1(Foreground buffer 1) R/W Virtual Screen OFFSIZE and PAGEWIDTH(Background buffer 1) R/W Virtual Screen OFFSIZE and PAGEWIDTH (Background buffer 2) R/W Virtual Screen OFFSIZE and PAGEWIDTH (Foreground buffer 1) R/W LCD Interrupt Control R/W COLOR KEY Control 1 R/W COLOR KEY Control 2 R/W Background color Control R/W Foreground color Control R/W LCD Dithering Control for Active Matrix Description Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0X4A00000C R/W LCD Time Control 2 0X4A00001C R/W Foreground image(OSD Image) Right Bottom position set 0X4A00002C R/W Frame Buffer Start Address 2(Foreground buffer 2) 0X4A00003C R/W Frame Buffer End Address 2(Foreground buffer 2) 0X4A00004C R/W Virtual Screen OFFSIZE and PAGEWIDTH (Foreground buffer 2) Individual Register Descriptions LCD Control 1 Register Register LCDCON1 28-18 Address 0X4A000000 R/W R/W Description LCD control 1 register Reset Value 0x00000000 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER LCDCON1 BURSTLEN Bit Description Initial State 0 [29:28] DMA's Burst Length selection : 00 : 16 word- burst 01 : 8 word- burst 10 : 4 word- burst 11 : reserved Reserved BDBCON [27:22] Reserved [21] Active Frame Select control for background image. It will be adopted from next frame data. 0 = Buffer1 1 = Buffer2 0 0 FDBCON [20] Active Frame Select control for foreground image(OSD image). It will be adopted from next frame data. 0 = Buffer1 1 = Buffer2 0 DIVEN [19] VCLK Divider( CLKVAL ) counter enable control bit 0 = Disable ( for Power saving) 1 = Enable 0 CLKVAL CLKDIR [18:13] Determine the rates of VCLK and CLKVAL[5:0]. VCLK = HCLK / [(CLKVAL+1) x 2] ( CLKVAL 0 ) [12] Select the clock source as direct or divide using CLKVAL register. 0 = Direct clock ( frequency of VCLK = frequency of Clock source) 1 = Divided using CLKVAL 0 0 Reserved PNRMODE [11] [10:9] This bit should be `0' Select the display mode. 00 = RGB Parallel mode ( RGB ) 01 = RGB Parallel mode ( BGR ) 10 = RGB Serial mode ( R->G->B) 11 = RGB Serial mode ( B->G->R) 0 0 BPPMODEF [8:6] Select the BPP (Bits Per Pixel) mode for foreground image (OSD). 011 = 8 BPP ( palettized ) 100 = 8 BPP ( non-palettized, R:3-G:3-B:2 ) 101 = 16 BPP ( non-palettized, R:5-G:6-B:5) 110 = 16 BPP ( non-palettized, R:5-G:5-B:5-I:1) 111 = unpacked 18 BPP ( non-palettized ) 0 BPPMODEB [5:2] Select the BPP (Bits Per Pixel) mode for background image. 0000 = 1 BPP 0001 = 2 BPP 0010 = 4 BPP 0 28-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR 0011 = 8 BPP ( palettized ) 0100 = 8 BPP ( non-palettized, R:3-G:3-B:2 ) 0101 = 16 BPP ( non-palettized, R:5-G:6-B:5) 0110 = 16 BPP ( non-palettized, R:5-G:5-B:5-I:1) 0111 = unpacked 18 BPP ( non-palettized ) 1xxx = Reserved ENVID [1] LCD video output and the logic immediately enable/disable. 0 = Disable the video output and the LCD control signal. 1 = Enable the video output and the LCD control signal. LCD video output and the logic enable/disable at current frame end. 0 = Disable the video output and the LCD control signal. 1 = Enable the video output and the LCD control signal. 0 ENVID_F [0] 0 * If you on and off this bit, then you will read "H" and video controller is enabled until the end of current frame. Note) Per Frame video on-off : ENVID & ENVID_F on-off simultaneously. Direct video on-off : ENVID on-off only. (where, ENVID_F = 0) LCD Control 2 Register Register LCDCON2 Address 0X4A000004 R/W R/W Description LCD control 2 register Reset Value 0x00000000 LCDCON2 LINECNT (read only) VSTATUS Bit [25:15] [14:13] Description Provide the status of the line counter (read only) Up count from 0 to LINEVAL Vertical Status (read only). 00 = VSYNC 10 = ACTIVE Horizontal Status (read only). 00 = HSYNC 10 = ACTIVE 00 = Reserved 10 = 16 bit (5:6:5) 01 = BACK Porch 11 = FRONT Porch Initial state 0 0 HSTATUS [12:11] 0 01 = BACK Porch 11 = FRONT Porch 0 01 = 18 bit ( 6:6:6) 11 = 16 bit ( 5:5:5:1) 0 0 PALFRM [10:9] This bit determines the size of the palette data format Reserved IVCLK [8] [7] This bit must be "0". This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge 1 = The video data is fetched at VCLK rising edge This bit indicates the HSYNC pulse polarity. 0 = normal 1 = inverted This bit indicates the VSYNC pulse polarity. 0 = normal 1 = inverted IHSYNC IVSYNC [6] [5] 0 0 28-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER Reserved IVDEN BITSWP BYTSWP HAWSWP [4] [3] [2] [1] [0] Reserved This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted Bit swap control bit. 0 = Swap Disable Byte swap control bit. 0 = Swap Disable 1 = Swap Enable 0 0 0 0 1 = Swap Enable 0 Half-Word swap control bit. 0 = Swap Disable 1 = Swap Enable LCD Time Control 1 Register Register LCDTCON1 Address 0X4A000008 R/W R/W Description LCD control 2 register Reset Value 0x00000000 LCDTCON1 VBPD VFPD VSPW Bit [23:16] [15:8] [7:0] Description Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. Vertical sync pulse width determines the VSYNC pulse's sync level width by counting the number of inactive lines. Initial State 0 0 0 LCD Time Control 2 Register Register LCDTCON2 Address 0X4A00000C R/W R/W Description LCD time control 2 register Reset Value 0x00000000 LCDTCON2 HBPD HFPD HSPW Bit [23:16] [15:8] [7:0] Description Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC. Horizontal sync pulse width determines the HSYNC pulse's sync level width by counting the number of the VCLK. Initial state 0000000 0X00 0X00 LCD Time Control 3 Register Register LCDTCON3 Address 0X4A000010 R/W R/W Description LCD time control 3 register Reset Value 0x00000000 LCDTCON3 Bit Description Initial state 28-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR LINEVAL HOZVAL [21:11] These bits determine the vertical size of LCD panel. [10:0] These bits determine the horizontal size of LCD panel. 0 0 LCD OSD Control 1 Register Register LCDOSD1 Address 0X4A000014 R/W R/W Description LCD OSD control 1 register Reset Value 0x00000000 LCDOSD1 OSDEN_F OSD_BLD_PIX [9] [8] Bit Description OSD(On-screen display) control bit. 0 = OSD Disable 1 = OSD Enable Select blending mode 0 = Per plane blending (8/16/18 BPP mode) 1 = Per pixel blending (18 BPP only) 0 0 Initial state OSD_ALPHA [7:0] 8-bit Alpha value for Per plane defined by Equation 28-1. 0 Note) OSD_ALPHA when blending mode is Per pixel should be written in MSB 8 bits of D[31:0]. If color key is enabled, blending function is not performed. LCD OSD Control 2 Register Register LCDOSD2 Address 0X4A000018 R/W R/W Description LCD OSD control 2 register Reset Value 0x0 LCDOSD2 OSD_LEFTTOP_X OSD_LEFTTOP_Y Bit [21:11] [10:0] Description Horizontal screen coordinate for left top pixel of OSD image Vertical screen coordinate for left top pixel of OSD image initial state 0 0 LCD OSD Control 3 Register Register LCDOSD3 Address 0X4A00001C R/W R/W Description LCD OSD control 3 register Reset Value 0x0 LCDOSD3 OSD_RIGHTBOT_X OSD_RIGHTBOT_Y Bit [21:11] [10:0] Description Horizontal screen coordinate for right bottom pixel of OSD image. OSD_RIGHTBOT_X <= LCD Panel size of X. initial state 0 0 Vertical screen coordinate for right bottom pixel of OSD image. OSD_RIGHTBOT_X <= LCD Panel size of Y. Note) Horizontal screen coordinate of LCDOSD2 and LCDOSD3 must be in word boundary. So, 18 BPP mode can has X position by 1 pixel. ( ex, X = 0,1,2,3....) 28-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER 16 BPP mode can has X position by 2 pixel. ( ex, X = 0,2,4,6....) 8 BPP mode can has X position by 4 pixel. ( ex, X = 0,4,8,12....) FRAME Buffer Start Address Registers Register LCDSADDRB1 LCDSADDRB2 LCDSADDRF1 LCDSADDRF2 Address 0X4A000020 0X4A000024 0X4A000028 0X4A00002C R/W Description Reset Value 0x0 0x0 0x0 0x0 R/W Frame buffer start address register for Background buffer 1 R/W Frame buffer start address register for Background buffer 2 R/W Frame buffer start address register for Foreground(OSD) buffer 1 R/W Frame buffer start address register for Foreground(OSD) buffer 2 LCDSADDRxx LCDBANK LCDBASEU Bit Description Initial State 0 0 [31:24] These bits indicate A[31:24] of the bank location for the video buffer in the system memory. [23:0] These bits indicate A[23:0] of the start address of the LCD frame buffer. FRAME Buffer End Address Registers Register Address R/W R/W R/W R/W R/W Description Frame buffer end address register for Background buffer 1 Frame buffer end address register for Background buffer 2 Frame buffer end address register for Foreground(OSD) buffer 1 Frame buffer end address register for Foreground(OSD) buffer 2 Reset Value 0x0 0x0 0x0 0x0 LCDEADDRB1 0X4A000030 LCDEADDRB2 0X4A000034 LCDEADDRF1 0X4A000038 LCDEADDRF2 0X4A00003C LCDEADDRxx LCDBASEL Bit [23:0] Description These bits indicate A[23:0] of the end address of the LCD frame buffer. LCDBASEL = LCDBASEU + (PAGEWIDTH+OFFSIZE) x (LINEVAL+1) Initial State 0x0000 Virtual Screen OffSIZE and PAGEWIDTH Registers Register Address R/W Description Reset Value 28-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR LCDVSCRB1 LCDVSCRB2 LCDVSCRF1 LCDVSCRF2 0X4A000040 0X4A000044 0X4A000048 0X4A00004C R/W R/W R/W R/W Virtual screen OFFSIZE and PAGEWIDTH for Background buffer 1 Virtual screen OFFSIZE and PAGEWIDTH for Background buffer 2 Virtual screen OFFSIZE and PAGEWIDTH for Foreground(OSD) buffer 1 Virtual screen OFFSIZE and PAGEWIDTH for Foreground(OSD) buffer 2 0x00000000 0x00000000 0x00000000 0x00000000 LCDVSCRxx OFFSIZE Bit Description Initial State 0 [25:13] Virtual screen offset size (the number of byte). This value defines the difference between the address of the last byte displayed on the previous LCD line and the address of the first byte to be displayed in the new LCD line. OFFSIZE must has value more than burst length value or 0. [12:0] Virtual screen page width (the number of byte). This value defines the width of the view port in the frame. PAGEWIDTH must has value which is multiple of the burst length. PAGEWIDTH 0 LCD Interrupt Control Register Register LCDINTCON Address 0X4A000050 R/W R/W Description Indicate the LCD interrupt control register Reset Value 0x0 LCDINTCON FRAMESEL0 Bit [11:10] 00 = BACK Porch 10 = ACTIVE Description LCD Frame Interrupt 2 at start of : 01 = VSYNC 11 = FRONT Porch Initial state 0 FRAMESEL1 [9:8] LCD Frame Interrupt 1 at start of : 00 = None 10 = VSYNC 01 = BACK Porch 11 = FRONT Porch 0 INTFRMEN [7] LCD Frame interrupt Enable control bit. 0 = LCD Frame Interrupt Disable 1 = LCD Frame Interrupt Enable 0 Reserved Reserved Reserved INTEN [6:5] [4:2] [1] [0] Reserved. Reserved. Reserved. LCD interrupt Enable control bit. 0 = LCD Interrupt Disable 1 = LCD Interrupt Enable 0 0 0 0 28-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER Color Key 1 Register Register LCDKEYCON Address 0X4A000054 R/W R/W Description Color key control register Reset Value 0x00000 LCDKEYCON KEYEN Bit [25] Description Color Key (Chroma key ) Enable control 0 = color key disable, blending enable 1 = color key enable, blending disable Initial state 0 DIRCON [24] Color key (Chroma key)direction control 0 = If the pixel value match foreground image with COLVAL according to COMPKEY, pixel from background image is displayed (only in OSD area) 1 = If the pixel value match background with COLVAL according to COMPKEY, pixel from foreground image is displayed (only in OSD area) 0 COMPKEY [23:0] Each bit is correspond to the COLVAL[23:0]. If some bit position is set then that bit position of COLVAL and pixel value will not be compared. 0 Color key 2 Register Register LCDCOLVAL Address 0X4A000058 R/W R/W Description Color key value ( transparent value) register Reset Value 0x00000000 LCDCOLVAL Bit Description Initial state 0 COLVAL [23:0] Color key value for the transparent pixel effect. Note) COLVAL and COMPKEY use 24bit data at all BPP mode. 18 BPP mode : 18 bit color value is valid. COLVAL 23 22 21 20 19 18 17-16 15 14 13 12 11 10 9-8 x 7 B5 6 B4 5 B3 4 B2 3 B1 2 B0 10 x Data R5 R4 R3 R2 R1 R0 x G5 G4 G3 G2 G1 G0 x: Don't care, We recommend that those bits are filled with `0'. COMPKE Y 23 22 21 20 19 18 17-16 15 14 13 12 11 10 9-8 7 B5 6 B4 5 B3 4 B2 3 B1 2 B0 1-0 0x3 Data R5 R4 R3 R2 R1 R0 0x3 G5 G4 G3 G2 G1 G0 0x3 COMPKEY[17:16], COMPKEY[9: 8] and COMPKEY[1:0] must be 0x3. 16 BPP (5:6:5) mode : 16 bit color value is valid 28-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR COLVAL 23 22 21 20 19 18-16 15 14 13 12 11 10 9-8 x 7 B5 6 B4 5 B3 4 B2 3 B1 20 x Data R5 R4 R3 R2 R1 x G5 G4 G3 G2 G1 G0 x: Don't care, We recommend that those bits are filled with `0'. COMPKE Y 23 22 21 20 19 18-16 15 14 13 12 11 10 9-8 7 B5 6 B4 5 B3 4 B2 3 B1 2-0 0x7 Data R5 R4 R3 R2 R1 0x7 G5 G4 G3 G2 G1 G0 0x3 COMPKEY[18:16] and COMPKEY[2:0] must be 0x7. COMPKEY[ 9: 8] must be 0x3. COMPKEY register must be set properly for the each BPP mode. Background Color MAP Register LCDBGCON Address 0X4A00005C R/W R/W Description Background color control Reset Value 0x00000 LCDBGCON BGCOLEN Bit [24] Description Background color mapping control bit . If this bit is enabled then lcd background DMA will stop, and GBCOLOR will be appear on background image instead of original image. 0 = disable 1 = enable Initial state 0 BGCOLOR [23:0] Color Value 0 Foreground Color MAP Register LCDFGCON Address 0X4A000060 R/W R/W Description Foreground color control Reset Value 0x00000 LCDFGCON FGCOLEN Bit [24] Description Foreground color mapping control bit . If this bit is enabled then lcd foreground DMA will stop, and FGCOLOR will be appear on foreground image instead of original image. 0 = disable 1 = enable Initial state 0 FGCOLOR 28-26 [23:0] Color Value 0 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR LCD CONTROLLER Dithering Control 1 Register Register LCDDITHMODE Address 0X4A000064 R/W R/W Description Dithering mode register. Reset Value 0x00000 LCDDITHMODE RDithPos Bit [6:5] Red Dither bit control 01 : 6bit 1x : 5bit Description Initial state 0 GDithPos [4:3] Green Dither bit control 01 : 6bit 1x : 5bit 0 BDithPos [2:1] Blue Dither bit control 01 : 6bit 1x : 5bit 0 DITHEN [0] Dithering Enable bit 0 = dithering disable 0 1 = dithering enable Note ) Dithering function can reduce the "contouring" effect. The "contouring" effect is a undesirable artifact which can be occurred at the following cases. - Reduce quantization ( pre-view of camera image) - Conversion of image data from YUV format to an RGB format - Edge boosting ( rigid line of 3D image ) - Etc. Notice: LCD controller use fixed dithering matrix, and it can occur the side artifact known as "graininess". So, user must make decision by trade-off between contouring effect and graininess effect. 28-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 LCD CONTROLLER S3C24A0 RISC MICROPROCESSOR Background Palette Ram Access Address (not SFR) Index 00 01 FF Address 0X4A001000 0X4A001004 0x4A0013FC R/W R/W R/W R/W Description Background Palette entry 0 address Background Palette entry 1 address Background Palette entry 255 address Reset Value undefined undefined undefined Foreground Palette Ram Access Address (not SFR) Index 00 01 FF Address 0X4A002000 0X4A002004 0x4A0023FC R/W R/W R/W R/W Description Foreground Palette entry 0 address Foreground Palette entry 1 address Foreground Palette entry 255 address Reset Value undefined undefined undefined 28-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR KEY PAD KEY PAD I/F (Preliminary) OVERVIEW The Key Pad I/F in S3C24A0 receives the key matrix inputs. An internal register remembers the last key pressed even after the key is released. It provides interrupt source and status register at the moment of key pressed or key released or both cases. The internal debouncing filter prevent the switching noises. The KEYDAT register value is the number of the pressed key. The number of 25 key is same as Figure 29-1. 0 SCAN_X[0] 5 10 15 20 S3C24A0 1 6 11 16 21 2 7 12 17 22 3 8 13 18 23 4 9 14 19 24 KEYIF SCAN_X[4] SCAN_Y[0] SCAN_Y[4] Figure 29-1. Key Matrix Interface Guide 29-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 KEY PAD S3C24A0 RISC MICROPROCESSOR KEYPAD CONTROL REGISTER KEYPAD CONTROL REGISTERS (KEYDAT, KEYPUP) Register KEYDAT address 0x44900000 R/W R/W Description The data register for KEYPAD input Reset Value 0x20 KEYDAT KEYDAT[3:0] KEYVAL Bit [4:0] [5] Description KEYPAD input decoding data (Read Only) KEYDAT Valid Status (Read Only) 0 = Valid 1 = Invalid Key Clear (Write Only) 0 = No action 1 = Clear the KEYDAT KEY Enable 0 = Disable KEYCLEAR [6] KEYEN [7] 1= Enable KEYPAD INTERRUPT CONTROL REGISTER Register KEYINTC address 0x44900004 R/W R/W Description KEYPAD input ports interrupt control Reset Value 0x0 KEYINTC KEYINTLV Bit [2:0] KEYINTEN [3] Description KEYPAD input ports interrupt level 000 = Low level (Key Pressing) 001=High level(Key Not Pressing) 010 = Rising edge(Key Released) 10x=Falling edge (Key Pressed) 11x = Both edge(Key Released or Key Pressed) Interrupt enable of KEYPAD input ports. 0 = disable 1= enable 29-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR KEY PAD DEBOUNCING FILTER FILTER_IN FILTER_OUT width = Filter_clk*(width_reg+1) KEYPAD FILTER CONTROL REGISTER ( KEYFLT ) Register KEYFLT0 KEYFLT1 Address 0x44900008 0x4490000C R/W R/W R/W Description KEY PAD Input Filter Control Register KEY PAD Input Filter Control Register Reset Value 0x0000 0x0000 KEYFLT0 SELCLK FILEN Reserved Bit [0] [1] [15:2] Description Select Filter Clock 0 = RTC Clock Filter Enable 0 = Disable Must be "0" 1 = GCLK 1= Enable KEYFLT1 WIDTH_reg Reserved Bit [13:0] [15:14] Description Filtering width of KEYPAD input ports. Must be "0" 29-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 KEY PAD S3C24A0 RISC MICROPROCESSOR KEYPAD MANUAL SCAN CONTROL REGISTER ( YMAN ) Register KEYMAN address 0x44900010 R/W R/W Description KEYPAD manual scan control Reset Value 0x1F YMAN Y_VAL MAN_EN Bit [4:0] [5] Description KEYPAD manual column value. (Read only) KEYPAD manual scan control enable 0 = disable 1= enable 29-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR A/D CONVERTER AND TOUCH SCREEN ADC & TOUCH SCREEN INTERFACE (PRELIMINARY) OVERVIEW The 10-bit CMOS ADC (Analog to Digital Converter) of S3C24A0 is a recycling type device with 8-channel analog inputs. It converts the analog input signal into 10-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz A/D converter clock. A/D converter operates with on-chip sample-and-hold function and power down mode is supported. S3C24A0 supports Touch Screen Interface. This function consists of touch screen panel, 4 internal switch, external voltage source, AIN[7] and AIN[5] (refer to the example, Figure 30-2). Touch Screen Interface is controlling and selecting control signal (nYPON, YMON, nXPON and XMON) and analog pads (AIN[7] and AIN[5]) which are connected with pads of touch screen panel and the internal switch for X-position conversion and Y-position conversion. Touch Screen Interface contains switch control logic and ADC interface logic with interrupt generation logic. FEATURES -- Resolution : 10-bit -- Differential Linearity Error : 1.0 LSB -- Integral Linearity Error -- Low Power Consumption -- Internal switch for X-position conversion and Y-position conversion -- Power Supply Voltage : 3.3V -- Analog Input Range : 0 ~ 3.3V -- On-chip sample-and-hold function -- Normal Conversion Mode -- Separate X/Y position conversion Mode -- Auto(Sequential) X/Y Position Conversion Mode -- Waiting for Interrupt Mode (Stylus pen up or down interrupt) : 2.0 LSB -- Maximum Conversion Rate : 500 KSPS 30-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 A/D CONVERTER AND TOUCH SCREEN S3C24A0 RISC MICROPROCESSOR ADC & TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 30-1 shows the functional block diagram of S3C24A0 A/D converter and Touch Screen Interface. Note that the A/D converter device is a recycling type. A pull-up resister is attached to AIN[7] on VDDA_ADC. So, XP pad of touch screen panel should be connected with AIN[7] of S3C24A0 and YP pad of touch screen panel should be connected with AIN[5]. nYPON YMON nXPON XMON VDDA_ADC AIN[7] AIN [6] AIN [5] AIN [4] AIN [3] AIN [2] AIN [1] AIN [0] VSSA_ADC 8:1 MUX Switch Matrix Internal Control Transister A/D Converter ADC interface &Touch Screen Controller ADC input control Waiting for Interrupt Interrup Generation INT_ADC INT_PENUP INT_PENDN Figure 30-1. ADC and Touch Screen Interface Functional Block Diagram 30-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR A/D CONVERTER AND TOUCH SCREEN EXAMPLE for touch screen In this example, AIN[7] is connected with XP and AIN[5] is connected with YP pad of touch screen panel. To control pads of touch screen panel (XP, XM, YP and YM), 4 internal transistor are applied and control signals, nYPON, YMON, nXPON and XMON are connected with 4 internal transistor. VDDA_ADC nYPON YMON nXPON Internal Transistor Control XMON XP XM YP YM A[7] A[6] A[5] A[4] Touch Panel S3C24A0 Figure 30-2. Example of ADC and Touch Screen Interface 1. Select Separate X/Y Position Conversion Mode or Auto (Sequential) X/Y Position Conversion Mode to get X/Y position. 2. Set Touch Screen Interface to Waiting Interrupt Mode, 3. If interrupt occurs, then appropriate conversion (Separate X/Y Position Conversion Mode or Auto (Sequential) X/Y Position Conversion Mode) is activated. 4. After get the proper value about X/Y position, return to Waiting for Interrupt Mode. 30-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 A/D CONVERTER AND TOUCH SCREEN S3C24A0 RISC MICROPROCESSOR FUNCTION DESCRIPTIONS A/D Conversion Time When the PCLK frequency is 50MHz and the prescaler value is 49, total 10-bit conversion time is as follows. A/D converter freq. = 50MHz/(49+1) = 1MHz Conversion time = 1/(1MHz / 5cycles) = 1/200KHz = 5 us NOTE: This A/D converter was designed to operate at maximum 2.5MHz clock, so the conversion rate can go up to 500 KSPS. Touch Screen Interface Mode 1. Normal Conversion Mode Normal Conversion Mode (AUTO_PST = 0, XY_PST = 0) is the most likely used for General Purpose ADC Conversion. This mode can be initialized by setting the ADCCON and ADCTSC and completed with a read the XPDATA (Normal ADC) value of ADCDAX (ADC Data Register 0). 2. Separate X/Y Position Conversion Mode Touch Screen Controller can be operated by one of two Conversion Modes. Separate X/Y Position Conversion Mode is operated as the following way; X-Position Mode (AUTO_PST = 0 and XY_PST = 1) writes X-Position Conversion Data to XPDATA of ADCDAX register, After conversion, Touch Screen Interface generates the Interrupt source (INT_ADC) to Interrupt Controller. Y-Position Mode (AUTO_PST = 0 and XY_PST = 2) writes Y-Position Conversion Data to YPDATA of ADCDAY, After conversion, Touch Screen Interface generates the Interrupt source (INT_ADC) to Interrupt Controller also. Table 30-1. Condition of touch screen panel pads in Separate X/Y Position Conversion Mode. XP X Position Conversion Y Position Conversion VDDA_ADC AIN[7] XM GND Hi-Z YP AIN[5] VDDA_ADC YM Hi-Z GND 30-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR A/D CONVERTER AND TOUCH SCREEN 1. Auto(Sequential) X/Y Position Conversion Mode Auto (Sequential) X/Y Position Conversion Mode (AUTO_PST = 1 and XY_PST = 0) is operated as the following; Touch Screen Controller automatically converts X-Position and Y-Position. Touch Screen Controller writes Xmeasurement data to XPDATA of ADCDAX, and then writes Y-measurement data to YPDATA of ADCDAY. After Auto (Sequential) Position Conversion, Touch Screen Controller is generating Interrupt source(INT_ADC) to Interrupt Controller. Table 30-2. Condition of touch screen panel pads in Auto (Sequential) X/Y Position Conversion Mode. XP X Position Conversion Y Position Conversion VDDA_ADC AIN[7] XM GND Hi-Z YP AIN[5] VDDA_ADC YM Hi-Z GND 1. Waiting for Interrupt Mode When Touch Screen Controller is in Waiting for Interrupt Mode (YM_SEN = 1, XP_SEN = 1 and XY_PST = 3), Touch Screen Controller is waiting for Stylus down or up. Touch Screen Controller is generating Interrupt (INT_PENDN or INT_PENUP) signal when the Stylus is down or up on Touch Screen Panel. After interrupt occurs, X and Y position can be read by the proper conversion mode (Separate X/Y position conversion Mode or Auto X/Y Position Conversion Mode). Table 30-3. Condition of touch screen panel pads in Waiting for Interrupt Mode. XP Waiting for Interrupt Mode AIN[7](Pull-up enable) XM Hi-Z YP AIN[5] YM GND Standby Mode Standby mode is activated when STDBM of ADCCON register is set to '1'. In this mode, A/D conversion operation is halted and XPDATA (Normal ADC) of ADCDAX and YPDATA of ADCDAY contain the previous converted data. 30-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 A/D CONVERTER AND TOUCH SCREEN S3C24A0 RISC MICROPROCESSOR Programming Notes 1. The A/D converted data can be accessed by means of interrupt or polling method. With interrupt method the overall conversion time - from A/D converter start to converted data read - may be delayed because of the return time of interrupt service routine and data access time. With polling method, by checking the ADCCON[15] - end of conversion flag-bit, the read time from ADCDAT register can be determined. Another way for starting A/D conversion is provided. After ADCCON[1] - A/D conversion start-by-read mode-is set to 1, A/D conversion starts simultaneously whenever converted data is read. 2. X-Conversion Y-Conversion XP Stylus Down Stylus Up YP A B C A = D x (1/X-Tal Clock) or A = D x (1/External Clock) B = D x (1/PCLK) C = D x (1/PCLK) D = DELAY value of ADCDLY Register Figure 30-3 Timing Diagram at Auto (Sequential) X/Y Position Conversion Mode 30-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR A/D CONVERTER AND TOUCH SCREEN ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS ADC CONTROL REGISTER (ADCCON) Register ADCCON Address 0x4580_0000 R/W R/W Description ADC Control Register Reset Value 0x3FC4 ADCCON ECFLG Bit [15] Description End of conversion flag(Read only) 0 = A/D conversion in process 1 = End of A/D conversion A/D converter prescaler enable 0 = Disable 1 = Enable Initial State 0 PRSCEN [14] 0 PRSCVL [13:6] A/D converter prescaler value Data value: 1 ~ 255 NOTE: ADC Freqeuncy should be set less than PCLK by 5times. (Ex. PCLK=10MHZ, ADC Freq.< 2MHz) Analog input channel select 000 = AIN 0 001 = AIN 1 010 = AIN 2 011 = AIN 3 100 = AIN 4 101 = AIN 5 (YP) 110 = AIN 6 111 = AIN 7 (XP) Standby mode select 0 = Normal operation mode 1 = Standby mode A/D conversion start by read 0 = Disable start by read operation 1 = Enable start by read operation A/D conversion starts by setting this bit. If READ_START is enabled, this value is not valid. 0 = No operation 1 = A/D conversion starts and this bit is cleared after the start-up. 0xFF SEL_MUX [5:3] 0 STDBM [2] 1 READ_ START [1] 0 ENABLE_START [0] 0 30-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 A/D CONVERTER AND TOUCH SCREEN S3C24A0 RISC MICROPROCESSOR ADC TOUCH SCREEN CONTROL REGISTER (ADCTSC) Register ADCTSC Address 0x4580_0004 R/W R/W Description ADC Touch Screen Control Register Reset Value 0x058 ADCTSC Reserved YM_SEN Bit [11:8] [7] Description Reserved. Should be set to 0. Select output value of YMON 0 = YMON output is 0. (YM = Hi-Z) 1 = YMON output is 1. (YM = GND) Select output value of nYPON 0 = nYPON output is 0. (YP = External voltage) 1 = nYPON output is 1. (YP is connected with AIN[5]) Select output value of XMON 0 = XMON output is 0. (XM = Hi-Z) 1 = XMON output is 1. (XM = GND) Select output value of nXPON 0 = nXPON output is 0. (XP = External voltage) 1 = nXPON output is 1. (XP is connected with AIN[7]) Pull-up Switch Enable 0 = XP Pull-up Enable. 1 = XP Pull-up Disable. Automatically sequencing conversion of X-Position and Y-Position 0 = Normal ADC conversion. 1 = Auto (Sequential) X/Y Position Conversion Mode. Manually measurement of X-Position or Y-Position. 00 = No operation mode 01 = X-position measurement 10 = Y-position measurement 11 = Waiting for Interrupt Mode Initial State 0 0 YP_SEN [6] 1 XM_SEN [5] 0 XP_SEN [4] 1 PULL_UP1) [3] 1 AUTO_PST2) [2] 0 XY_PST3) [1:0] 0 NOTE: 1. Unexpected pen-up or pen-down interrupt may be occurred when pull-up switch is turn on. It is recommended that pull-up enable switch is turn on before setting to the waiting for interrupt mode because some stabilization time of pull-up switch is needed. 2. AUTO_PST bit should be set whenever the data conversion ends if the conversion start by read mode is activated. 3. When all data conversions are finished at automatically sequencing conversion mode, the conversion pointer remained at Y position conversion mode. It is recommended to set XY_PST register to "01" (X-position measurement mode) every conversion time for getting right result. 30-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR A/D CONVERTER AND TOUCH SCREEN ADC START DELAY REGISTER (ADCDLY) Register ADCDLY Address 0x4580_0008 R/W R/W Description ADC Start or Interval Delay Register Reset Value 0x00ff ADCDLY DELAY Bit [15:0] Description 1) Normal Conversion Mode, Separate X/Y Position Conversion Mode, Auto (Sequential) X/Y Position Conversion Mode. X/Y Position Conversion Delay Value. 2) Waiting for Interrupt Mode. When Stylus down occurs at Waiting for Interrupt Mode, generates Interrupt signal (INT_ADC), having interval (several ms), for Auto X/Y Position conversion. Note) Don't use Zero value(0x0000) Initial State 00ff NOTE: 1. Before ADC conversion, Touch screen uses X-tal clock or EXTCLK (Waiting for Interrupt Mode). 2. During ADC conversion PCLK is used. 30-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 A/D CONVERTER AND TOUCH SCREEN S3C24A0 RISC MICROPROCESSOR ADC CONVERSION DATA REGISTER (ADCDAX) Register ADCDAX Address 0x4580_000C R/W R Description ADC Conversion Data Register X-Position conversion data at Touch Screen mode Reset Value - ADCDAX UPDOWN Bit [15] Description Up or Down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state. 1 = Stylus up state. Automatic sequencing conversion of X-Position and Y-Position 0 = Normal ADC conversion. 1 = Sequencing measurement of X-position, Y-position. Manually measurement of X-Position or Y-Position. 00 = No operation mode 01 = X-position measurement 10 = Y-position measurement 11 = Waiting for Interrupt Mode Initial State - AUTO_PST [14] - XY_PST [13:12] - Reserved XPDATA (Normal ADC) [11:10] [9:0] Reserved X-Position Conversion data value (include Normal ADC Conversion data value) Data value : 0 ~ 3FF - 30-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR A/D CONVERTER AND TOUCH SCREEN ADC CONVERSION DATA REGISTER (ADCDAY) Register ADCDAY Address 0x4580_0010 R/W R Description ADC Conversion Data Register Y-Position conversion data at Touch Screen mode Reset Value - ADCDAY UPDOWN Bit [15] Description Up or Down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state. 1 = Stylus up state. Automatically sequencing conversion of X-Position and Y-Position 0 = Normal ADC conversion. 1 = Sequencing measurement of X-position, Y-position. Manually measurement of X-Position or Y-Position. 00 = No operation mode 01 = X-position measurement 10 = Y-position measurement 11 = Waiting for Interrupt Mode Initial State - AUTO_PST [14] - XY_PST [13:12] - Reserved YPDATA [11:10] [9:0] Reserved Y-Position Conversion data value Data value : 0 ~ 3FF - 30-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 A/D CONVERTER AND TOUCH SCREEN S3C24A0 RISC MICROPROCESSOR NOTES 30-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDI SECURE DIGITAL INTERFACE OVERVIEW The S3C24A0 SDI(Secure Digital Interface) can interface for SD memory card, SDIO device and MMC(MultiMedia Card). FEATURE SD Memory Card Spec(Ver 1.0) / MMC Spec(2.11) compatible SDIO Card Spec(Ver 1.0) compatible 16 words(64 bytes) FIFO for data Tx/Rx 40-bit Command Register 136-bit Response Register 8-bit Prescaler logic(Freq = System Clock / (P + 1)) Normal, and DMA data transfer mode(byte, halfword, word transfer) DMA burst4 access support(only word transfer) 1bit / 4bit(wide bus) mode & block / stream mode switch support 31-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SDI S3C24A0 RISC MICROPROCESSOR BLOCK DIAGRAM 32 PADDR 32 CMD Reg (5byte) Resp Reg (17byte) 8 CMD Control 8bit Shift Reg TxCMD RxCMD 8 PSEL PCLK PWDATA 32 [31:0] PRDATA 32 [31:0] APB I/F 32 CRC7 Prescaler 8 SDCLK DAT Control 32bit Shift Reg TxDAT[3:0] RxDAT[3:0] 32 FIFO (64byte) 8 CRC16*4 DREQ DACK INT DMA INT Figure 31-1. SDI Block Diagram 31-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDI SDI OPERATION A serial clock line synchronizes shifting and sampling of the information on the five data lines. The transmission frequency is controlled by making the appropriate bit settings to the SDIPRE register. You can modify its frequency to adjust the baud rate data register value. Programming Procedure (common) To program the SDI modules, follow these basic steps: 1. Set SDICON to configure properly with clock & interrupt enable 2. Set SDIPRE to configure with a proper value. 3. Wait 74 SDCLK clock cycle in order to initialize the card. CMD Path Programming 1. Write command argument 32bit to SDICARG. 2. Determine command types and start command transmit with setting SDICCON. 3. Confirm the end of SDI CMD path operation when the specific flag of SDICSTA is set 4. The flag is CmdSent if command type is no response. 5. The flag is RspFin if command type is with response. 6. Clear the corresponding flag of SDICSTA through writing one with this bit DAT Path Programming 1. Write data timeout period to SDIDTIMER. 2. Write block size(block length) to SDIBSIZE(normally 0x80 word). 3. Determine the mode of block, wide bus, dma, etc and start data transfer with setting SDIDCON. 4. Tx data Write data to Data Register(SDIDAT) while Tx FIFO is available(TFDET is set), or half(TFHalf is set), or empty(TFEmpty is set). 5. Rx data Read data from Data Register(SDIDAT) while Rx FIFO is available(RFDET is set), or full(RFFull is set), or half(RFHalf is set), or ready for last data(RFLast is set). 6. Confirm the end of SDI DAT path operation when DatFin flag of SDIDSTA is set 7. Clear the corresponding flag of SDIDSTA through writing one with this bit 31-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SDI S3C24A0 RISC MICROPROCESSOR SDIO OPERATION There are two functions of SDIO operation: SDIO Interrupt receiving and Read Wait Request generation. These two functions can operate when RcvIOInt bit and RwaitEn bit of SDICON register is activated respectively. And two functions have the steps and conditions like below. SDIO Interrupt In SD 1bit mode, Interrupt is received through all range from RxDAT [1] pin. In SD 4bit mode, RxDAT[1] pin is shared between data receiving and interrupt receiving. When interrupt detection range (Interrupt Period) is: 1. Single Block : the time between A and B A : 2clocks after the completion of a data packet B : The completion of sending the end bit of the next withdata command 2. Multi Block, PrdType = 0 : the time between A and B, restart at C A : 2clocks after the completion of a data packet B : 2clocks after A C : 2clocks after the end bit of the abort command response 3. Multi Block, PrdType = 1 : the time between A and B, restart at A A : 2clocks after the completion of a data packet B : 2clocks after A In case of last block, interrupt period begins at A, but not ends at B(CMD53 case) Read Wait Request Regardless of 1bit or 4bit mode, Read Wait Request signal transmits to TxDAT[2] pin in condition of below. In read multiple operation, request signal transmission begins at 2clocks after the end of the data block Transmission ends when user sets to one RwaitReq bit of SDIDSTA register 31-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDI SDI SPECIAL REGISTERS SDI Control Register (SDICON) Register SDICON Address 0x4600_0000 Bit [31:9] [8] [7:6] R/W R/W Description SDI Control Register Description Reset whole sdmmc block. This bit is automatically clear. 0 = normal mode, 1 = SDMMC reset Determines how much you delay CMD, DAT lines for hold margin in MMC clock type 00 = 1/2 PCLK cycle, 01 = 1 PCLK cycle 10 = 3/2 PCLK cycles, 11 = 2 PCLK cycles Determines which clock type is used as SDCLK. 0 = SD type, 1 = MMC type Determines byte order type when you read(write) data from(to) sd host FIFO with word boundary. 0 = Type A, 1 = Type B Determines whether sd host receives SDIO Interrupt from the card or not(for SDIO). 0 = ignore, 1 = receive SDIO Interrupt Determines read wait request signal generate when sd host waits the next block in multiple block read mode. This bit needs to delay the next block to be transmitted from the card(for SDIO). 0 = disable(no generate), 1 = Read wait enable(use SDIO) Determines whether SDCLK Out enable or not 0 = disable(prescaler off), 1 = clock enable Reset Value 0x0 Initial Value 0 0 SDICON Reserved SDMMC Reset (SDreset) Hold Margin (HoldMgn) Clock Type (CTYP) Byte Order Type(ByteOrder) Receive SDIO Interrupt from card (RcvIOInt) Read Wait Enable(RWaitEn) [5] [4] 0 0 [3] 0 [2] 0 Reserved Clock Out Enable (ENCLK) * Byte Order Type [1] [0] 0 - Type A: (Access by Word) D[7:0] D[15:8] D[23:16] D[31:24] (Access by Halfword) D[7:0] D[15:8] - Type B: (Access by Word) D[31:24] D[23:16] D[15:8] D[7:0] (Access by Halfword) D[15:8] D[7:0] SDI Baud Rate Prescaler Register (SDIPRE) Register SDIPRE Address 0x4600_0004 Bit [7:0] R/W R/W Description SDI Buad Rate Prescaler Register Reset Value 0x01 Initial Value 0x01 Description Determines SDI clock (SDCLK) rate as above equation. Baud rate = PCLK / (Prescaler value + 1) * Prescaler Value should be greater than zero. SDIPRE Prescaler Value 31-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SDI S3C24A0 RISC MICROPROCESSOR SDI Command Argument Register (SDICARG) Register SDICARG SDICARG CmdArg Address 0x4600_0008 Bit [31:0] R/W R/W Description SDI Command Argument Register Description Command Argument Reset Value 0x0 Initial Value 0x00000000 SDI Command Control Register (SDICCON) Register SDICCON Address 0x4600_000c Bit [31:13] [12] [11] [10] [9] [8] R/W R/W Description SDI Command Control Register Description Determines whether command type is for abort(for SDIO). 0 = normal command, 1 = abort command(CMD12, CMD52) Determines whether command type is with data(for SDIO). 0 = without data, 1 = with data Determines whether host receives a 136-bit long response or not 0 = short response, 1 = long response Determines whether host waits for a response or not 0 = no response, 1 = wait response Determines whether command operation starts or not. . This bit is automatically clear 0 = command ready, 1 = command start Command index with start 2bit(8bit) Reset Value 0x0 Initial Value 0 0 0 0 0 SDICCON Reserved Abort Command (AbortCmd) Command with Data (WithData) LongRsp WaitRsp Command Start(CMST) CmdIndex [7:0] 0x00 31-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDI SDI Command Status Register (SDICSTA) Register SDICSTA SDICSTA Reserved Response CRC Fail(RspCrc) Command Sent (CmdSent) Command Time Out (CmdTout) Response Receive End (RspFin) CMD line progress On (CmdOn) RspIndex Address 0x4600_0010 Bit [31:13] [12] R/C [11] R/C [10] R/C [9] R/C [8] [7:0] R/W R/(C) Description SDI Command Status Register Description CRC check failed when command response received. This flag is cleared by setting to one this bit. 0 = not detect, 1 = crc fail Command sent(not concerned with response). This flag is cleared by setting to one this bit. 0 = not detect, 1 = command end Command response timeout(64clk). This flag is cleared by setting to one this bit. 0 = not detect, 1 = timeout Command response received. This flag is cleared by setting to one this bit. 0 = not detect, 1 = response end Command transfer in progress 0 = not detect, 1 = in progress Response index 6bit with start 2bit(8bit) Reset Value 0x0 Initial Value 0 0 0 0 0 0x00 SDI Response Register0 (SDIRSP0) Register SDIRSP0 SDIRSP0 Response0 Address 0x4600_0014 Bit [31:0] R/W R Description SDI Response Register 0 Reset Value 0x0 Initial Value 0x00000000 Description Card status[31:0](short), card status[127:96](long) SDI Response Register1 (SDIRSP1) Register SDIRSP1 SDIRSP1 RCRC7 Response1 Address 0x4600_0018 Bit [31:24] [23:0] R/W R Description SDI Response Register 1 Reset Value 0x0 Initial Value 0x00 0x000000 Description CRC7(with end bit, short), card status[95:88](long) unused(short), card status[87:64](long) SDI Response Register2 (SDIRSP2) Register SDIRSP2 SDIRSP2 Response2 Address 0x4600_001c Bit [31:0] R/W R Description SDI Response Register 2 Reset Value 0x0 Initial Value 0x00000000 Description unused(short), card status[63:32](long) 31-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SDI S3C24A0 RISC MICROPROCESSOR SDI Response Register3 (SDIRSP3) Register SDIRSP3 SDIRSP3 Response3 Address 0x4600_0020 Bit [31:0] R/W R Description SDI Response Register 3 Reset Value 0x0 Initial Value 0x00000000 Description unused(short), card status[31:0](long) SDI Data / Busy Timer Register (SDIDTIMER) Register SDIDTIMER SDIDTIMER Reserved DataTimer Address 0x4600_0024 Bit [31:21] [22:0] R/W R/W Description SDI Data / Busy Timer Register Description Data / Busy timeout period(0~2M cycle) Reset Value 0x0 Initial Value 0x10000 SDI Block Size Register (SDIBSIZE) Register SDIBSIZE Address 0x4600_0028 R/W R/W Description SDI Block Size Register Reset Value 0x0 Initial Value 0x000 SDIBSIZE Bit Description Reserved [31:12] BlkSize [11:0] Block Size value(0~4095 byte) , don't care when stream mode * In Case of multi block, BlkSize must be aligned to word (4byte) size. (BlkSize[1:0] = 00) 31-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDI SDI Data Control Register (SDIDCON) Register SDIDCON SDIDCON Reserved Burst4 enable (Burst4) Address 0x4600_002c Bit [31:25] [24] R/W R/W Description SDI Data control Register Description Reset Value 0x0 Initial Value 0 Enable Burst4 mode in DMA mode. This bit should be set only when Data Size is word. 0 = disable, 1 = Burst4 enable 0 Data Size [23:22] Indicates the size of the transfer with FIFO, which is typically byte, (DataSize) halfword or word. 00 = Byte transfer, 01 = Halfword transfer 10 = Word transfer, 11 = reserved SDIO Interrupt [21] Determines whether SDIO Interrupt period is 2 cycle or extend 0 Period Type more cycle when last data block is transferred(for SDIO). (PrdType) 0 = exactly 2 cycle, 1 = more cycle(likely single block) Transmit After [20] Determines when data transmit start after response receive or not 0 Response 0 = directly after DatMode set, (TARSP) 1 = after response receive(assume DatMode sets to 2'b11) Receive After [19] Determines when data receive start after command sent or not 0 Command 0 = directly after DatMode set, (RACMD) 1 = after command sent (assume DatMode sets to 2'b10) [18] Determines when busy receive start after command sent or not 0 Busy After Command 0 = directly after DatMode set, (BACMD) 1 = after command sent (assume DatMode sets to 2'b01) Block mode [17] Data transfer mode 0 (BlkMode) 0 = stream data transfer, 1 = block data transfer Wide bus enable [16] Determines enable wide bus mode 0 (WideBus) 0 = standard bus mode(only SDIDAT[0] used), 1 = wide bus mode(SDIDAT[3:0] used) DMA Enable [15] Enable DMA 0 (EnDMA) 0 = disable(polling), 1 = dma enable Data Transfer [14] Determines whether data transfer start or not. . This bit is auto0 Start(DTST) matically clear 0 = data ready, 1 = data start Data Transfer [13:12] Determines which direction of data transfer 00 Mode (DatMode) 00 = no operation, 01 = only busy check start 10 = data receive start, 11 = data transmit start BlkNum [11:0] Block Number(0~4095), don't care when stream mode 0x000 * If you want one of TARSP, RACMD, BACMD bits (SDIDCON [20:18]) to "1", you need to write on SDIDCON register ahead of on SDICCON register. (Always need for SDIO) 31-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SDI S3C24A0 RISC MICROPROCESSOR SDI Data Remain Counter Register (SDIDCNT) Register SDIDCNT SDIDCNT Reserved BlkNumCnt BlkCnt Address 0x4600_0030 Bit [31:24] [23:12] [11:0] R/W R Description SDI Data Remain Counter Register Description Remaining Block number Remaining data byte of 1 block Reset Value 0x0 Initial Value 0x000 0x000 SDI Data Status Register (SDIDSTA) Register SDIDSTA Address 0x4600_0034 Bit [31:12] [11] R/C [10] R/C [9] R/C [8] [7] R/C [6] R/C [5] R/C [4] R/C [3] R/C [2] [1] [0] R/W R/(C) Description SDI Data Status Register Description Busy is not active during 16cycle after cmd packet transmitted in only busy check mode. This flag is cleared by setting to 1 this bit. 0 = not detect, 1 = no busy signal Read wait request signal transmits to sd card. The request signal is stopped and this flag is cleared by setting to one this bit. 0 = not occur, 1 = Read wait request occur SDIO interrupt detect. This flag is cleared by setting to one this bit. 0 = not detect, 1 = SDIO interrupt detect CRC Status error when data block sent(CRC check failed). This flag is cleared by setting to one this bit. 0 = not detect, 1 = crc status fail Data block received error(CRC check failed). This flag is cleared by setting to one this bit. 0 = not detect, 1 = receive crc fail Data / Busy receive timeout. This flag is cleared by setting to one this bit. 0 = not detect, 1 = timeout Data transfer completes (data counter is zero). This flag is cleared by setting to one this bit. 0 = not detect, 1 = data finish detect Only busy check finish. This flag is cleared by setting to one this bit 0 = not detect, 1 = busy finish detect Data transmit in progress 0 = not active, 1 = data Tx in progress Data receive in progress 0 = not active, 1 = data Rx in progress Reset Value 0x0 Initial Value 0 SDIDSTA Reserved No Busy(NoBusy) Read Wait Request Occur (RWaitReq) SDIO Interrupt Detect(IOIntDet) Reserved CRC Status Fail(CrcSta) Data Receive CRC Fail(DatCrc) Data Time Out(DatTout) Data Transfer Finish(DatFin) Busy Finish (BusyFin) Reserved Tx Data progress On(TxDatOn) Rx Data Progress On(RxDatOn) 0 0 0 0 0 0 0 0 0 0 31-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDI SDI FIFO Status Register (SDIFSTA) Register SDIFSTA Address 0x4600_0038 Bit [31:16] [16] C [15:14] R/C R/W R Description SDI FIFO Status Register Description Reset FIFO value. This bit is automatically clear. 0 = normal mode, 1 = FIFO reset FIFO fail error when FIFO occurs overrun / underrun data saving. This flag is cleared by setting to one these bits. 00 = not detect, 01 = FIFO fail 10 = FIFO fail in the last transfer(only FIFO reset need) 11 = reserved This bit indicates that FIFO data is available for transmit when DatMode is data transmit mode. If DMA mode is enable, SD host requests DMA operation. 0 = not detect(FIFO full), 1 = detect(0 FIFO 63) This bit indicates that FIFO data is available for receive when DatMode is data receive mode. If DMA mode is enable, sd host requests DMA operation. 0 = not detect(FIFO empty), 1 = detect(1 FIFO 64) This bit sets to 1 whenever Tx FIFO is less than 33byte. 0 = 33 Tx FIFO 64, 1 = 0 Tx FIFO 32 This bit sets to 1 whenever Tx FIFO is empty. 0 = 1 Tx FIFO 64, 1 = Empty(0byte) This bit sets to 1 when Rx FIFO occurs to behave last data of all block. This flag is cleared by setting to one this bit. 0 = not received yet, 1 = Rx FIFO gets Last data This bit sets to 1 whenever Rx FIFO is full. 0 = 0 Rx FIFO 63, 1 = Full(64byte) This bit sets to 1 whenever Rx FIFO is more than 31byte. 0 = 0 Rx FIFO 31, 1 = 32 Rx FIFO 64 Number of data(byte) in FIFO Reset Value 0x0 Initial State 0 0 SDIFSTA Reserved FIFO Reset(FRST) FIFO Fail error (FFfail) FIFO available Detect for Tx (TFDET) FIFO available Detect for Rx (RFDET) Tx FIFO Half Full (TFHalf) Tx FIFO Empty (TFEmpty) Rx FIFO Last Data Ready (RFLast) Rx FIFO Full (RFFull) Rx FIFO Half Full (RFHalf) [13] 0 [12] 0 [11] [10] [9] R/C [8] [7] 0 0 0 0 0 FIFO Count [6:0] 0000000 (FFCNT) * Although the last Rx data size is lager than remained count of FIFO data, you could read this data. If this event happens, you should clear FFfail field, and FIFO reset field 31-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 SDI S3C24A0 RISC MICROPROCESSOR SDI Interrupt Mask Register (SDIIMSK) Register SDIIMSK Address 0x4600_003C R/W R/W Description SDI Interrupt Mask Register Reset Value 0x0 Initial Value 0 0 0 SDICON Reserved NoBusy Interrupt Enable (NoBusyInt) RspCrc Interrupt Enable (RspCrcInt) CmdSent Interrupt Enable (CmdSentInt) CmdTout Interrupt Enable (CmdToutInt) RspEnd Interrupt Enable (RspEndInt) RWaitReq Interrupt Enable (RWReqInt) IOIntDet Interrupt Enable (IntDetInt) FFfail Interrupt Enable (FFfailInt) CrcSta Interrupt Enable (CrcStaInt) DatCrc Interrupt Enable (DatCrcInt) DatTout Interrupt Enable (DatToutInt) DatFin Interrupt Enable (DatFinInt) BusyFin Interrupt Enable(BusyFinInt) Reserved TFHalf Interrupt Enable (TFHalfInt) TFEmpty Interrupt Enable(TFEmptInt) RFLast Interrupt Enable (RFLastInt) RFFull Interrupt Enable (RFFullInt) RFHalf Interrupt Enable (RFHalfInt) Bit Description [31:19] [18] Determines SDI generate an interrupt if busy signal is not active 0 = disable, 1 = interrupt enable [17] Determines SDI generate an interrupt if response CRC check fails 0 = disable, 1 = interrupt enable [16] Determines SDI generate an interrupt if command sent(no response required) 0 = disable, 1 = interrupt enable [15] Determines SDI generate an interrupt if command response timeout occurs 0 = disable, 1 = interrupt enable [14] Determines SDI generate an interrupt if command response received 0 = disable, 1 = interrupt enable [13] Determines SDI generate an interrupt if read wait request occur. 0 = disable, 1 = interrupt enable [12] Determines SDI generate an interrupt if sd host receives SDIO Interrupt from the card(for SDIO). 0 = disable, 1 = interrupt enable [11] Determines SDI generate an interrupt if FIFO fail error occurs 0 = disable, 1 = interrupt enable [10] Determines SDI generate an interrupt if CRC status error occurs 0 = disable, 1 = interrupt enable [9] Determines SDI generate an interrupt if data receive CRC failed 0 = disable, 1 = interrupt enable [8] Determines SDI generate an interrupt if data receive timeout occurs 0 = disable, 1 = interrupt enable [7] Determines SDI generate an interrupt if data counter is zero 0 = disable, 1 = interrupt enable [6] Determines SDI generate an interrupt if only busy check completes 0 = disable, 1 = interrupt enable [5] [4] Determines SDI generate an interrupt if Tx FIFO fills half 0 = disable, 1 = interrupt enable [3] Determines SDI generate an interrupt if Tx FIFO is empty 0 = disable, 1 = interrupt enable [2] Determines SDI generate an interrupt if Rx FIFO has last data 0 = disable, 1 = interrupt enable [1] Determines SDI generate an interrupt if Rx FIFO fills full 0 = disable, 1 = interrupt enable [0] Determines SDI generate an interrupt if Rx FIFO fills half 0 = disable, 1 = interrupt enable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR SDI SDI Data Register (SDIDATn) Register SDIDAT0 SDIDAT1 SDIDAT2 SDIDAT3 SDIDATn Data Register Address 0x4600_0040(W,HW,B) 0x4600_0044(Word) 0x4600_0048(Word) 0x4600_004C(Word) Bit [31:0] R/W R/W R/W R/W R/W Description SDI Data0 Register SDI Data1 Register SDI Data2 Register SDI Data3 Register Reset Value 0x0 0x0 0x0 0x0 Description Initial State This field contains the data to be transmitted or received over the 0x00000000 SDI channel * In case that DMA Burst4 mode is enabled by setting SDIDCON [24], SDIDAT1 ~ SDIDAT3 are valid. 31-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MEMORY STICK MEMORY STICK (Preliminary) OVERVIEW There are so many types of media for storing and transferring data. Memory Stick is one of the popular media. The S3C24A0 supports Memory Stick specifications version 1.3. Four pins are dedicated for memory stick interface, which are Bus State (MS_BS), Serial Data (MS_SDIO), Serial Clock (MS_SCLK) and Insertion Detect (MS_INS). FEATURES _ _ _ _ _ _ _ _ _ _ Protocol is stared by writing to the command register (TP_CMD) Supports DMA BUSY timeout period can be controlled by setting the BSYCNT bit fields in control status register (CTRL_STA) 16-bit access The output from FIFO is only little endian Built in 8-byte (2-word) FIFO buffers for Tx and Rx respectively Built in CRC circuit (can be turned on/ off) PCLK must be under 80MHz Supports automatic command execution (can be turn on/ off) Supports Memory Stick detection interrupt 32-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MEMORY STICK S3C24A0 RISC MICROPROCESSOR MEMORY STICK PROTOCOL Figure 32-1and 2 shows the read/ write packet of Memory Stick. The memory stick host controller uses only PCLK as its source clock. The MS_SCLK frequency is made by divided PCLK (1/1, 1/2, 1/4 or 1/8) and it is slower than 20MHz. BS0 BS1 BS2 BS3 BS0 IN T Memory Stick TP C DATA Host CR C RDY/BSY IN T Memory StIck Figure 32-1. Memory stick write packet BS0 BS1 BS2 BS3 BS0 IN T Memory Stick TP C Host RDY/BSY DATA CR C IN T Memory StIck Figure 32-2. Memory stick read packet MANDATORY HARDWARE CONFIGURATION The MS_SDIO pin should be configured pull down resistor and the MS_INS pin should be configured pull up resistor. 32-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MEMORY STICK HOST BLOCK PIN DESCRIPTION Pin name XINT Function name Interrupt request Dir Out Active Low Description Interrupt request signal line Low level during interrupt request High level at access to IntDataReg Parallel port for input only (used for insertion/extraction detect of Memory stick) Fixed in a High level when unused High level when receive data buffer is empty Low level when there is data in receive data buffer High level when receive data buffer is full. Low level when there is space in receive data buffer High level when transmit data buffer is empty Low level when there is data in transmit data buffer High level when transmit data buffer is full Low level when there is space in transmit data buffer PI Input parallel Port In - RBE Receive Buffer Empty Out High RBF Receive Buffer Full Out High TBE Transmit Buffer Empty Out High TBF Transmit Buffer Full Out High Interrupt control SIEN INT_STA check INT_SIF(RO) INT_P_END(RO) INT_EN INT_TOE(RO) NOCRC INT_CRC(RO) XINT Host Controller SDIO INS INT_INS(RO) INS_EN PI BS FIFO Control INS_INTEN RBF(RO) RBE(RO) TBF(RO) TBE(RO) SCLK FIFO_INT 32-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MEMORY STICK S3C24A0 RISC MICROPROCESSOR MEMORY STICK SPECIAL REGISTERS PRESCALER CONTROL (MSPRE) REGISTER Register MSPRE Address 0x46100000 R/W R/W Description Pescaler control register Reset Value 0x0 MSPRE PRE_EN PRE_VAL Bit [2] [1:0] Prescaler control 0 = Disable Prescaler value 00 = 1/1 10 = 1/4 Description 1 = Enable Initial State 0 00 01 = 1/2 11 = 1/8 Note: MS_SCLK must be less than 20MHz FIFO INTERRUPT CONTROL (MSFINTCON) REGISTER Register MSFINTCON Address 0x46100004 R/W R/W Description FIFO interrupt control Reset Value 0x0 MSINTCON FIFO_INTEN Bit [0] Description FIFO states, which are receive buffer full (RBF), receive buffer empty (RBF), transmit buffer full (TBF) and transmit buffer empty (TBF) request interrupt or do not. 0 = Only for XINT 1 = Enables interrupt request according to FIFO states Note: XINT means internal conditions, which are detecting protocol end interrupt (INT_P_END), serial interface interrupt (INT_SIF), Tx/ Rx request interrupt (INT_TR), and insertion interrupt (INT_INS). Initial State 0 32-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MEMORY STICK TRANSFER PROTOCOL COMMAND (TP_CMD) REGISTER Register TP_CMD Address 0x46108000 R/W R/W Description Transfer protocol command register Reset Value 0x0000 MSINTCON TPC Bit [15:12] Description Transfer protocol command 0x2 = Read page data 0xd = Write page data 0x8 = Set read/ write register address 0xe = Set command 0x7 = Get interrupt 0x4 = Read register 0xb = Write register Others = Reserved Note: These bit fields can not be written while the INT_P_END bit in INTCON_STA register is `0'. Initial State 0x0 Reserved DAT_SIZE [11:10] [9:0] Reserved Transferred data size 0x200 = Read/ write page data command 0x4 = Set read/ write register address 0x1 = Set command/ Get interrupt 0xX = Any data size to read/ write register 00 0x00 32-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MEMORY STICK S3C24A0 RISC MICROPROCESSOR CONTROL AND STATUS (CTRLSTA) REGISTER Register CTRL_STA Address 0x46108004 R/W R/W Description Control [15:8] and staus [7:0] register Reset Value 0x050a MSCTRLSTA RST PWS SIEN Reserved NOCRC BSYCNT Bit [15] [14] [13] [12] [11] [10:8] 0 = Clear reset 0 = Normal mode 0 = Disable Should be 0 (SBZ) Description Internal logic reset control 1 = Reset Power save mode control 1 = Power save mode Serial interface enable/ disable control 1 = Enable Initial State 0 0 0 0 0 0x5 CRC enable/ disable control 0 = Enable Busy timeout counter Timeout detecting time (MS_SCLK cycles) = BSYCNT x 4 + 2 Example: BSYCNT = 0x5, MS_SCLK = 10MHz Exceeding 2.2us (22 x 0.1) causes a RDY timeout error. 1 = Disable INT_STA (Read only) DRQ_STA (Read only) Reserved RBE_STA (Read only) RBF_STA (Read only) TBE_STA (Read only) TBF_STA (Read only) [7] Interrupt status 0 = Not generated interrupt condition 1 = Generated interrupt condition 0 [6] DMA request status 0 = Not requested DMA 1 = Requested DMA 0 [5:4] [3] Reserved Receive buffer (FIFO) empty status 0 = Not empty 1 = Empty 00 1 [2] Receive buffer (FIFO) full status 0 = Not full 1 = Full 0 [1] Transmit buffer (FIFO) empty status 0 = Not empty 1 = Empty 1 [0] Transmit buffer (FIFO) full status 0 = Not full 1 = Full 0 32-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MEMORY STICK DATA FIFO (DAT_FIFO) REGISTER Memory stick host controller has two 16-byte FIFO for the Tx and Rx mode. Transmit and receive FIFO access is performed through same FIFO entry: the address FIFOENTY is 0x46108008. Register DAT_FIFO Address 0x46108008 R/W R/W Description Tx/ Rx FIFO (buffer) register Reset Value 0x0000 MSFIFO FIFOENTRY Bit [15:0] Description Transmit/ Receive data for Memory Stick Initial State 0x0000 32-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MEMORY STICK S3C24A0 RISC MICROPROCESSOR INTERRUPT CONTROL AND STATUS (INTCTRLSTA) REGISTER Register INTCTRL_STA Address 0x4610800c R/W R/W Description Interrupt control [15:8] and staus [7:0] register Reset Value 0x0080 MSINTCTRLSTA INT_EN Reseved INS_INTEN Reserved INT_P_END (Read only) INT_SIF (Read only) Reseved INT_INS (Read only) Reserved INT_CRC (Read only) INT_TOE (Read only) Bit [15] [14] [13] [12:8] [7] [6] [5] [4] [3:2] [1] [0] 0 = Disable Reseved Description Internal enable/ disable control 1 = Enable Initial State 0 0 0 0x00 1 0 0 0 Insertion interrupt enable/ disable control 0 = Disable Reserved Protocol end interrupt status 0 = In progress 0 = No interrupt Reseved Insertion interrupt status 0 = No insertion Reserved CRC error interrupt status 0 = No CRC error 0 = No timeout error 1 = Occurred CRC error Busy timeout error interrupt status 1 = Occurred timeout error 1 = Insertion 1 = Complete 1 = Receive interrupt Serial interface receive interrupt status(From Memory stick) 1 = Enable 00 0 0 32-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR MEMORY STICK INS PORT CONTROL (INSCON) REGISTER Register INS_CON Address 0x46108010 R/W R/W Description INS port control register Reset Value 0x0000 MSINSCON Reserved INS_EN Reserved INS_STA Reserved Bit [15:13] [12] [11:5] [4] [3:0] Reserved Description INS port enable/ disable control 0 = Disable Reserved INS port status 0 = High (no insertion) 1 = Low (insertion) Reserved 1 = Enable Initial State 000 0 0x00 0 0x0 32-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 MEMORY STICK S3C24A0 RISC MICROPROCESSOR AUTO COMMAND/ POL CONTROL (ACMD_CON) REGISTER Register ACMD_CON Address 0x46108014 R/W R/W Description Auto command and polaity control register Reset Value 0x0000 MSACMDCON ATPC_EN POL Reserved Bit [15] [14] [13:0] 0 = Disable 0 = Rising edge Reserved Description Auto command operation enable/ disable control 1 = Enable Loading polarity control of the serial data input 1 = Falling edge Initial State 0 0 0x00 AUTO TRANSFER PROTOCOL COMMAND (ATP_CMD) REGISTER Register ATP_CMD Address 0x46108018 R/W R/W Description Auto transfer protocol command register Reset Value 0x7001 MSACMD ATPC Reserved ADAT_SIZE Bit [15:12] [11:10] [9:0] Description Set transfer protocol command (TPC) to be automatically executed. Reserved Set the size of data which is transferred. Initial State 0x7 0x0 0x01 32-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CLOCK & POWER MANAGEMENT OVERVIEW The clock & power management unit consists of 3 parts; System Clock Control, USB Clock Control, and System Power-management Control. The System Clock Control logic in S3C24A0 can generate the required system clock signals, ARMCLK for CPU, HCLK for the AHB-bus peripherals, and PCLK for the APB-bus peripherals. There are two PLLs in S3C24A0. One is for ARMCLK, HCLK, and PCLK, and the other is for the USB, IrDA and Camera Interface. The clock controllogic can make slow clock without PLL and connect/disconnect the clock to each peripheral block by software, which will reduce the power consumption. In the power control logic, S3C24A0 has various power management schemes to keep optimal power consumption for a given task. The power management in S3C24A0 consists of four modes: General Clock Gating (NORMAL) mode, IDLE mode, STOP mode, and SLEEP mode. General Clock Gating mode is used to control the On/Off of clocks for internal peripherals in S3C24A0. The user can optimize the power consumption of S3C24A0 using this General Clock Gating mode by supplying clocks for peripherals that are necessary for a certain application. For example, if a timer is not needed, the user can disconnect the clock to the timer to reduce power. IDLE mode disconnects the ARMCLK only to CPU core while it supplies the clock to all peripherals. By using IDLE mode, the power consumption due to CPU core can be reduced. STOP mode freezes all clocks to the CPU as well as peripherals by disabling PLLs. The power consumption is only due to the leakage current in S3C24A0. SLEEP mode is intended to disconnect the internal power. So, the power consumption due to CPU and the internal logic except the wake-up logic will be zero in the SLEEP mode. In order to use the SLEEP mode two independent power sources are needed. One of the two power sources supplies the power for the wake-up logic. The other one supplies the other internal logic including CPU, and should be controlled in order to be turned on/off. In SLEEP mode, the second power supply source for the CPU and internal logic will be turned off. A detailed description of the power-saving modes such as the entering sequence to the specific power-down mode or the wake-up sequence from a power-down mode is given in the following Power Management section. 33-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 CLOCK & POWER MANAGEMENT S3C24A0 RISC MICROPROCESSOR FUNCTION DESCRIPTION CLOCK Generation Overview Figure 33-1 shows the block diagram of the clock generation module. The main clock source comes from an external crystal (XsXTIN) or external clock (XsEXTCLK). The clock generator consists of two PLLs (PhaseLocked-Loop) which generate the high-frequency clock signals required in S3C24A0. XgREFCLKSEL[1] MPLL_clk XsXTIN MPLL (M_M/ P/ S) CLKDIVN (H/ P/ M) HCLK PCLK MPEGCLK XgREFCLKSEL[0] UPLL_clk XsXTIN UPLL (U_M/ P/ S) 0 ExtclkDiv 0 CLKDIVN (C) ClockIdle ARMCLK CAMCLK 1/2 IrDACLK 0 1/2 USBCLK XsEXTCLK XsEXTCLK Figure 33-1. Clock Generator Block Diagram CLOCK Source Selection Table 33-1 shows the relationship between the combination of mode control pins XgREFCLKSEL[1:0] and the selection of source clock for S3C24A0. (see the figure 33-1.) Table33-1. Clock source selection for the internal PLLs and clock generation logic XgREFCLKSEL[1:0] (refer to Pin Description) 00 01 10 11 NOTES. 1. Although the MPLL/UPLL starts just after a reset, the MPLL output (MPLL_clk) isn't used as the system clock until the S/W writes valid settings to the MPLLCON / UPLLCON register. Before this valid setting, the clock from XsXTIN or XsEXTCLK source will be used as the system clock directly. Even if the user wants to maintain the default value of MPLLCON / UPLLCON register, the user should write the same value into MPLLCON / UPLLCON register. MPLL generates the clock source for ARMCLK, HCLK, PCLK and UPLL generates clock source for USBCLK, IrDACLK and CAMCLK. Main Clock source (MPLL and External Clock) XsXTIN XsXTIN XsEXTCLK XsEXTCLK USB Clock source (UPLL and External Clock) XsXTIN XsEXTCLK XsXTIN XsEXTCLK 2. 33-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT PLL (Phase-Locked-Loop) The PLL (Phase-Locked Loop) frequency synthesizer is constructed in CMOS on single monolithic structure. The PLL provides frequency multiplication capabilities the output clock frequency MPLL_clk is related to the input clock frequency Fin by the following equation: Fout (MPLL_clk or UPLL_clk) = (m * Fin) / (p * 2s) Where, m = M (the value for Main Divider)+ 8, p = P(the value for Pre-Divider P) + 2 Where, Fout is the output clock frequency. Fin the input frequency. M, P and S are the values for programmable dividers (see the register description). The PLL consists of a Phase/Frequency Detector (PFD), a Charge Pump, an Off-chip Loop Filter, a Voltage Controlled Oscillator (VCO), a 6 bit pre-divider, an 8bit main divider and 2-bit post scaler and shown in Fig.33-2 The UPLL within the clock generator is same as the MPLL in every aspect. To ensure the proper operation of the internal PLLs, we recommend the following PLL value-sets(refer to table 33-7). If the user requires other range of PLL set-values, please contact one of SEC application engineers. Off-chip loop filter Fin PreDivider(P) PFD Charge Pump VCO Post Scaler(S) Fout Main Divider(M) Figure 33-2. PLL (Phase-Locked Loop) Block Diagram 33-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 CLOCK & POWER MANAGEMENT S3C24A0 RISC MICROPROCESSOR Usual Conditions for PLL & Clock Generator Table 33-2. Recommended operation conditions Characteristics Supply voltage differential External loop filter capacitance Operating temperature -40 Min -0.1 1.7 85 Typ Max 0.1 Unit V nF C Table 33-3. DC Electrical Characteristics Characteristics Operating voltage Dynamic current Power down current Symbol AVDD12D/AVDD12A LDD lPD TBD Min 1.14 Typ 1.20 Max 1.26 3 Unit V mA A Table 33-4. AC Electrical Characteristics Characteristics Input frequency Output clock frequency VCO output frequency Input clock duty cycle Input glitch pulse width Jitter, cycle to cycle Symbol FIN Fout FVCO TID TIGP TJCC 200 Min 10 50 100 40 50 Typ Max 40 300 300 60 1 200 Unit MHz MHz MHz % ns ps CLOCK Control Logic The clock control logic determines the clock source to be used, i.e., the PLL clock(MPLL_clk) or the direct external clock ( XsXTIN or XsEXTCLK ). When PLL is configured to a new frequency value, the clock control logic disables the ARMCLK until the PLL output is stabilized during the PLL locking time. The clock control logic is also activated at power-on reset and waked-up from power-down mode. PLL Lock Time The lock time is the minimum time required for PLL output stabilization. The lock time should be a minimum of 300us. After reset and wake-up from STOP and SLEEP mode, respectively, the lock-time is inserted automatically by the internal logic with lock time count register. The automatically inserted lock time is calculated as follows; t_lock (the PLL lock time by H/W logic) = (1/ Fin) x n where, n = M_LTIME for MPLL,U_LTIME for UPLL, refer to the register description 33-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Power-On Reset (XsRESETn) Figure 33-3 shows the clock behavior during the power-on reset sequence. The crystal oscillator begins oscillation within several milliseconds after the power source supplies enough power-level to the S3C24A0. Internal PLLs (MPLL and UPLL) also begins the frequency locking based on power-on-reset frequency-setting value. XsRESETn signal should be released after the fully settle-down of the power-level. For the proper system operation, the S3C24A0 requires a hazard-free system clock (ARMCLK, HCLK and PCLK) when the system reset is released (XsRESETn). However, the PLL is commonly known to be unstable after power-on reset, so Fin (the direct external clock source, XsXTIN or XsEXTCLK depending on the XgREFCLKSEL[1:0] pin status) is fed directly to ARMCLK instead of the MPLL_clk (PLL output) before the S/W newly configures the MPLLCON register. Even if the user wants to use the default value of MPLLCON register, user should write the same value into MPLLCON register by S/W after the release of the system reset. The PLL begins the lockup sequence toward the new frequency only after the S/W configures the PLL with a new frequency-value. ARMCLK is configured to be PLL output (MPLL_clk) immediately after lock time. The user should be aware that the crystal oscillator settle-down time is not explicitly added by the hardware during the power-up sequence. The S3C24A0 assumes that the crystal oscillation is settled during the power-supply settle-down period. However, to ensure the proper operation during wake-up from the STOP mode, the S3C24A0 explicitly adds the crystal oscillator settle-down time (the wait-time can be programmed using the XTALWSET registers) after wake-up from the STOP mode. For the USB, IrDA and Camera Interface device clocks, the output of UPLL clock is directly fed to those devices. Power XsRESETn XsEXTCLK or XsXTIN PLL is configured by S/W first time. Clock Disable lock time VCO is adapted to new clock frequency. VCO output ARMCLK The logic operates by XsEXTCLK or XsXTIN ARMCLK is new frequency Figure 33-3. Power-On Reset Sequence 33-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 CLOCK & POWER MANAGEMENT S3C24A0 RISC MICROPROCESSOR Change PLL Settings In Normal Operation During the operation of S3C24A0 in NORMAL mode, if the user wants to change the frequency by writing the PMS value, the PLL lock time is automatically inserted. During the lock time, the clock is not supplied to the internal blocks in S3C24A0. The timing diagram is as follow. MPLL_clk PMS setting PLL Lock-time ARMCLK It changes to new PLL clock after lock time automatically Figure 33-4. The case that changes Slow clock by setting PMS value NOTE : Changing PMS value can cause a problem in LCD display. In the S3C24A0, the LCD screen-refresh timing is dependent on the HCLK (HCLK clock is also dependent on the MPLL clock output). ARMCLK, HCLK, PCLK, MPEGCLK and CAMCLK Control The ARMCLK is used for ARM926EJ-S core, the main CPU of the S3C24A0. The HCLK is the reference clock for internal AHB bus and peripherals such as the memory controller, the interrupt controller, the Modem Interface, LCD controller, the DMA, USB host block, System Controller, Power down controller and etc. The PCLK is used for internal APB bus and peripherals such as WDT, IIS, I2C, PWM timer, and MMC interface, ADC, UART, GPIO, RTC and SPI etc. MPEGCLK is used for MPEG4 H/W accelerator block such as DCT, ME, MC block. CAMCLK is used for camera interface block. The following table shows the clock division ratios between ARMCLK, HLCK and PCLK. This ratio is determined by HDIV and PDIV bits of CLKDIVN control register. HCLKdiv[1:0] 00 00 01 01 10 10 PCLKdiv 0 1 0 1 0 1 ARMCLK ARMCLK ARMCLK ARMCLK ARMCLK ARMCLK ARMCLK HCLK ARMCLK ARMCLK ARMCLK / 2 ARMCLK / 2 ARMCLK / 4 ARMCLK / 4 PCLK ARMCLK ARMCLK / 2 ARMCLK / 2 ARMCLK / 4 ARMCLK / 4 ARMCLK / 8 Division Ratio 1 : 1 : 1 (Default) 1:1:2 1:2:2 1:2:4 1:4:4 1:4:8 33-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT MPEGCLK and CAMCLK frequency are determined by MPEGCLKdiv[3:0] and CAMCLKdiv[3:0] bits of CLKDIVN control register. MPEG or CAMCLKdiv[3:0] 0 1~15 MPEGCLK HCLK HCLK / ( 2 x MPEGCLKdiv ) CAMCLK UPLL_clk / 2 UPLL_clk / (CAMCLKdiv + 1 ) * 2 The MPEGCLK and the CAMCLK frequency are changed whenever the source clock frequency is changed. UCLK (USB Clock) Control USB host interface and USB device interface needs 48Mhz fixed-frequency clock. In the S3C24A0, The USB dedicated PLL (UPLL) generates 96Mhz and divided by two for USB block. UPLL will be turned off during STOP and SLEEP mode automatically. Also, UPLL will be generated clock to USBCLK, IrDACLK, CAMCLK after exiting STOP and SLEEP mode if USBon, IrDAclkOn and CAMclkOn bits are enabled in CLKCON register. Condition After reset After configuring UPLL UPLL is turned off by U_PLLoff bit in CLKSRC register UPLL is turned on by U_PLLoff bit in CLKSRC register UCLK state UPLL Output During PLL lock time: Low After PLL lock time: UPLL Output No Clock UPLL Output off on UPLL State on on NOTE: UPLL_clk (UPLL output) is 98MHz. USBCLK is obtained by dividing by two of UPLL_clk, i.e. UPLL_clk/2. 33-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 CLOCK & POWER MANAGEMENT S3C24A0 RISC MICROPROCESSOR Power Management The power management block controls the system clocks by software for the reduction of power consumption in S3C24A0. These schemes are related to PLL, clock control logic(ARMCLK,HCLK,PCLK) and wake-up signal. The Figure 33-5 depicts the clock distribution of S3C24A0. S3C24A0 has four power-down modes. The following section describes each power management mode. VPOST ARM926-EJ System Configuration Registers MPLL_out ARMclk MPEG4IF Fin PLL (Main & USB) Clock Generation (on/ off control) MPEGclk HCLK PCLK UPLLclk LCD CAMIF UPLL_out VPOSTIF System Configuration Registers USB Host MPEG4ME MPEG4DCTQ VLX AC97 PWM TIMER UART0 UART1 SPI I2C I2S GPIO USB Device Memory Stick USB IrDA CAM SD ADC Key Pad Figure 33-5. The Clock Distribution Block Diagram 33-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT POWER SAVING MODES General Clock Gating Mode In General Clock Gating mode, the On/Off clock gating of the individual clock source of each IP block is performed by controlling of each corresponding clock source enable bit. The Clock Gating is applied instantly whenever the corresponding bit (or bits) is changed. (In general, these bits are set or cleared by the main CPU.) IDLE Mode In IDLE mode, the clock to CPU core is stopped. The IDLE mode is activated just after the execution of the STR instruction that enables the IDLE Mode bit. The IDLE Mode bit should be cleared by software after the wake-up from the IDLE state because it is not cleared automatically, and the H/W logic only detects the low-to-high triggering of the IDLE Mode bit. STOP Mode In STOP mode, all clocks are stopped for minimum power consumption. Therefore, the PLL and oscillator circuit are also stopped. The STOP Mode is activated after the execution of the STR instruction that enables the STOP Mode bit. The STOP Mode bit should be cleared by software after the wake-up from the STOP state because it is not cleared automatically, and the H/W logic only detects the low-to-high triggering of the STOP Mode bit. To exit from STOP mode, External interrupt, RTC alarm, Touch Screen Pen-down INT, Modem INT, XsRESETn or XsWRESETn has to be activated. During the wake-up sequences, the crystal oscillator and PLL may begin to operate. The crystal-oscillator settle-down-time and the PLL locking-time is required to provide stabilized ARMCLK. Those time-waits are automatically inserted by the hardware of the S3C24A0. During these time-waits, the clock is not supplied to the internal logic circuitry. STOP mode Entering sequence is 1) Set the STOP Mode bit by software. 2) Set the SDRAM in self-refresh mode to preserve its contents (the Power-manager of S3C24A0 requests the entering of the self-refresh state to the SDRAM controller of S3C24A0 and it issues the self-refresh command.) 3) After receiving the self-refresh acknowledge, disables the X-tal and PLL oscillation. STOP mode Exiting sequence is 1) Enable X-tal Oscillator if it is used, and wait the OSC settle down (around 1ms). 2) After the Oscillator settle-down, the System Clock is fed using the PLL input clock and also enable the PLLs and waits the PLL locking time. 3) Switching the clock source, now the PLL is the clock source. 4) The SDRAM controller releases the self-refresh mode just before the S3C24A0 access the SDRAM. NOTES: 1. 2. DRAM has to be in self-refresh mode during STOP and SLEEP mode to retain valid memory data. LCD must be stopped before STOP and SLEEP mode, because DRAM can't be accessed when it is in self-refresh mode. 33-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 CLOCK & POWER MANAGEMENT S3C24A0 RISC MICROPROCESSOR XsXTIN or XsEXTCLK a Wake-up Clock Disable XTALWSET VCO Output lock time ARMCLK STOP mode is initiated. Figure 33-6. Entering STOP Mode and Exiting STOP mode (Wake-up) SLEEP Mode In the SLEEP Mode, all the clock sources are off and also the internal logic-power is not supplied except for the wake-up logic circuitry. In this mode, the static power-dissipation of internal logic can be minimized. SLEEP Mode Entering sequence is as follows. 1) One of the SLEEP Mode entering events is triggered by the system software or by the hardware. 2) Set the SDRAM in self-refresh mode to preserve its contents (the Power-manager of S3C24A0 requests the entering of the self-refresh state to the SDRAM controller of S3C24A0 and it issues the self-refresh command.). 3) After receiving the self-refresh acknowledge, disables the X-tal and PLL oscillation and also disables the external power source for the internal logic by asserting XgPWROFFn signal to low state. XgPWROFFn signal is the regulator-disable control signal for the internal-logic power-source. SLEEP Mode Exiting sequence is as follows. 1) Enable external power source by deactivation of the XgPWROFFn signal and wait power settle down time (around 6ms, it is programmable by a register in the GPIO block). 2) Release the System Reset (synchronously, relatively to the system clock) after the power supply is stabilized (see the GPIO descriptions). 3) The SDRAM controller releases the self-refresh mode just before the S3C24A0 access the SDRAM. 33-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Power Mode State Diagram Figure 33-7 show that Power Saving mode state and Entering or Exiting condition. In general, the S3C24A0 issues the Entering conditions. CMD Normal (General Clock Gating Mode) One of wakeup source One of wakeup source CMD IDLE CMD or nBATFLT nBATFLT SLEEP Reset or restricted wakeup evants. STOP nBATFLT Figure 33-7. Power mode state diagram Wake-Up Event When the S3C24A0 wakes up from the STOP Mode or the SLEEP Mode by an External Interrupt, a RTC alarm interrupt and other interrupts, the PLL is turned on automatically. However, the clock supply scheme is quite different. The initial-state of the S3C24A0 after wake-up from the SLEEP Mode is almost the same as the PowerOn-Reset state except for the contents of the external DRAM is preserved. In contrast, the S3C24A0 automatically recovers the previous working state after wake-up from the STOP Mode. The following table shows the states of PLLs and internal clocks after wake-ups from the power-saving modes. Table 33-5. The Status of PLL and ARMCLK After Wake-Up Mode before wake-up IDLE STOP SLEEP PLL on/off after wake up Unchanged Off on Off on ARMCLK after wake up and before the lock time PLL Output No clock External Clock ARMCLK after the lock time by internal logic PLL Output PLL Output External Clock Output port state in STOP and SLEEP mode Refer to Pin Assignment Table * in Product Overview chapter. 33-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 CLOCK & POWER MANAGEMENT S3C24A0 RISC MICROPROCESSOR Power Saving Mode Entering/Exiting Condition Table 33-6 shows that Power Saving mode state and Entering or Exiting condition. Table 33-6. Power Saving Mode Entering/Exiting condition Power Saving Mode NORMAL IDLE Entering Disable the CLKCON bit for each IP block Enable the ClockIdle bit of CLKCON register Exiting Enable the CLKCON bit for each IP block 1) External INT[9:0] 2) RTC Alarm INT 3) Touch Screen Pen-down INT 4) Modem INT 5) XsWRESETn 6) XsRESETn 1) External INT[9:0] 2) RTC Alarm INT 3) Touch Screen Pen-down INT 4) Modem INT 5) XsWRESETn 6) XsRESETn STOP Enable the ClockStop bit of CLKCON register SLEEP Write `0xA3' to the SLEEP_CODE[7:0] bits 1) External INT[9:0] of PWRMAN register 2) RTC Alarm INT 3) XsWRESETn 4) XsRESETn When the XgBATFLT port goes to low 1) External INT: GPIO[1:0] 2) XsWRESETn 3) XsRESETn SLEEP NOTES: 1. The Wake-up Event Sources for the SLEEP mode due to the XgBATFLT are limited as in the above table. 2. Entering to the SLEEP mode by the XgBATFLT is programmable, 1) the XgBATFLT can be forwarded as an FIQ 2) the XgBATFLT can be used as the entering event for the SLEEP mode 3) the XgBATFLT can be ignored. Reset Definition Reset XsRESETn Definition This is the cold reset. The internal state (include registers) of the S3C24A0 will be initialized when XsRESETn is activated. The XsRESETn is a non-maskable signal except for the case when the XgBATFLTn is in the active state (low). The contents of the SDRAM will not be preserved when the XsRESETn is applied. The XsWRESETn and the Soft-reset reset the system except RTC, Clock Generator, power management module and memory controller (preserves SDRAM data) XsWRESETn, SoftReset 33-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER (LOCKTIME) Register LOCKTIME LOCKTIME U_LTIME M_LTIME Address 0x40000000 Bit [27:16] [11:0] R/W R/W Description PLL lock time count register Description UPLL lock time count (generally 300us) MPLL lock time count (generally 300us) Reset Value 0x0FFF_0FFF Initial State 0xFFF 0xFFF PLL Locking Time Locking Time = (1/Fin) * (U_LTIME or M_LTIME * 16) X-TAL OSCILLATION WAIT REGISTER (XTALWSET) Register XTALWSET Address 0x40000004 R/W R/W Description Crystal oscillator settle-down wait time Reset Value 0x5000_5000 XTALWSET U_OSCWAIT M_OSCWAIT Bit [31:16] [15:0] Description UPLL Crystal oscillator settle-down wait time MPLL Crystal oscillator settle-down wait time Initial State 0x5000 0x5000 X-tal Settle-down wait time X-tal Settle-down Time = Tcrystal_clock * (U_OSCWAIT or M_OSCWAIT) 33-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 CLOCK & POWER MANAGEMENT S3C24A0 RISC MICROPROCESSOR PLL CONTROL REGISTER (MPLLCON, UPLLCON) PLL value selection guide 1. Mpll or Upll = (m * Fin) / (p * 2s), where: m = (MDIV + 8), p = (PDIV + 2), s = SDIV 2. Fin/(25*p) < 16.7e6/m < Fin/(10*p) 3. 0.7 < 6.48/sqrt(m) < 1.8 4. (Fin/p)*m < 330e6 Register MPLLCON UPLLCON M/U PLLCON MDIV PDIV SDIV Address 0x40000010 0x40000014 Bit [19:12] [9:4] [1:0] R/W R/W R/W Description MPLL configuration register UPLL configuration register Description Main divider control ( M value ) Pre-divider control ( P value ) Post divider control ( S value ) Reset Value 0x0004_8021 0x0003_0021 Initial State 0x48 / 0x30 0x02 / 0x02 0x1 / 0x1 To ensure the proper operation of the internal PLLs, we recommend the following PLL value-sets. If the user requires other range of PLL set-values, please contact one of SEC application engineers. Table 33-7 PLL value selection table Input Frequency 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz Output Frequency (MHz) 84 90 96 102 112.5 118 124 132 136 176 177 180 186 192 200 204 MDIV 34 (0x22) 37 (0x25) 56 (0x38) 43 (0x2b) 67 (0x43) 51 (0x33) 54 (0x36) 58 (0x3a) 60 (0x3c) 36 (0x24) 51 (0x33) 37 (0x25) 54 (0x36) 56 (0x38) 42 (0x2a) 60 (0x3c) PDIV 1 1 2 1 2 1 1 1 1 1 2 1 2 2 1 2 SDIV 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 33-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CLOCK CONTROL REGISTER (CLKCON) Register CLKCON CLKCON VLXclkOn VPOSTclkOn Reserved MPEGDCTQclkOn VPOSTIFclkOn MPEGIFclkOn CAMclkOn LCDclkOn CAMIFclkOn MPEGMEclkOn KeyPadClkOn ADCclkOn SDclkOn MSclkOn USBdeviceClkOn GPIOclkOn IISclkOn IICclkOn SPIclkOn Address 0x40000020 Bit [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] R/W R/W Description Clock generator control Register Description Controls HCLK into VLX block 0: Disable 1: Enable Controls MPEGCLK into VPOST block 0: Disable 1: Enable Reserved Controls MPEGCLK into MPEGDCTQ block 0: Disable 1: Enable Controls HCLK into VPOST block (AHB bus side) 0: Disable 1: Enable Controls HCLK into MPEG AHB Interface 0: Disable 1: Enable Controls UPLL_clk into CAM block 0: Disable 1: Enable Controls HCLK into LCD block 0: Disable 1: Enable Controls HCLK into camera interface block 0: Disable 1: Enable Controls MPEG4CLK into MPEG ME block 0: Disable 1: Enable Controls PCLK into Key Pad block 0: Disable 1: Enable Controls PCLK into ADC block 0: Disable 1: Enable Controls PCLK into SD block 0: Disable 1: Enable Controls PCLK into Memory Stick block 0: Disable 1: Enable Controls PCLK into USB device block 0: Disable 1: Enable Controls PCLK into GPIO block 0: Disable 1: Enable Controls PCLK into IIS block 0: Disable 1: Enable Controls PCLK into IIC block 0: Disable 1: Enable Controls PCLK into SPI block 0: Disable 1: Enable 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset Value 0x03fffff0 Initial State 1 1 33-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 CLOCK & POWER MANAGEMENT S3C24A0 RISC MICROPROCESSOR CLKCON UART1clkOn UART0clkOn PWMTIMERClkOn USBhostClkOn AC97clkOn Reserved IrDAclkOn Reserved ClockIdle ClkMonOn ClockStop Bit [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description Controls PCLK into UART1 block 0: Disable 1: Enable Controls PCLK into UART0 block 0: Disable 1: Enable Controls PCLK into PWMTIMER block 0: Disable 1: Enable Controls HCLK into USB host block 0: Disable 1: Enable Controls PCLK into AC97 block 0: Disable 1: Enable Reserved(Should be zero) Controls UPLL_clk into IrDA block 0: Disable 1: Enable Reserved Enters IDLE mode. This bit is not cleared automatically. 0: Disable 1: Transition to IDLE mode HCLK monitor Enable 0: Disable 1: Enable Enters STOP mode. This bit is not cleared automatically. 0: Disable 1: Transition to STOP mode Initial State 1 1 1 1 1 0 1 0 0 0 0 CLOCK SOURCE CONTROL REGISTER (CLKSRC) Register CLKSRC Address 0x40000024 R/W R/W Description Clock source control register. Reset Value 0x00000004 CLKSRC OnOSC_EN U_PLLoff Reserved M_PLLoff SelExtClk Reserved ExtclkDiv Bit [8] [7] [6] [5] [4] [3] [2:0] Description Crystal Oscillator Enable control during the STOP mode 0: Disable 1: Enable UPLL on/off control 0: on 1: off Reserved MPLL on/off control 0: on 1: off Select External clock source for ARMCLK/HCLK/PCLK 0: MPLL_clk 1: External clock Reserved External clock division factor 000: No division001 ~ 110: Divided by (2*ExtClkDiv) 111: Reserved for the S3C24A0 test Initial State 0 0 0 0 0 0 4 33-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CLOCK DIVIDER CONTROL REGISTER (CLKDIVN) Register CLKDIVN Address 0x40000028 R/W R/W Description Clock divider control register Reset Value 0x0000_0300 CLKDIVN CAMclkdiv MPEGclkdiv HCLKdiv Bit [11:8] [7:4] [2:1] CAMclk Division Factor MPEGclk Division Factor HCLK Division Factor Description Initial State 0x5 0 0 00: ARMCLK: HCLK = 1:1 01: ARMCLK: HCLK = 1:2 10: ARMCLK: HCLK = 1:3 11: ARMCLK: HCLK = 1:4 PCLKdiv [0] 0: PCLK has the clock same as the HCLK 1: PCLK has the clock same as the HCLK/2 0 POWER MANAGEMENT CONTROL REGISTER (PWRMAN) Register PWRMAN PWRMAN USE_WFI Address 0x40000030 Bit [12] R/W R/W Description Power management register Description Use the WFI (wait for interrupt) instruction before enter into stop and sleep mode. If this bit is set, the power management block checks the internal signal (STANDBYWFI), so WIF instruction must be added by software. 0: Not use MASK_MODEM CNFG_BF [11] [10:9] 1: Use the WFI 0 0x0 Baseband Modem wakeup mask setting register 0: Unmask 1: Mask Battery fault handling configuration setting register 00: Emergency Sleep 10: Ignore MASK_TS SLEEP_CODE NOTE: 1. 2. SLEEP_CODE is 0xA3. When this register was set with the value of 0xXXXX_XXA3 the SLEEP mode is activated. When using the WFI instruction in the ARM926EJ-S core by setting the USE_WFI bit, the entering sequence of power-saving mode is as follows, a. b. Set the ClockStop bit in CLKCON register or write sleep code to SLEEP_CODE bits in PWRMAN register. Execute the WFI instruction Reset Value 0x0000_1000 Initial State 1 01: FIQ 11: reserved 0 1: Mask [8] [7:0] Touch screen wakeup mask setting register 0: Unmask SLEEP Mode setting code 33-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 CLOCK & POWER MANAGEMENT S3C24A0 RISC MICROPROCESSOR Softreset Control register (SOFTRESET) Register SOFTRESET SOFTRESET Soft Reset Address 0x40000038 Bit [7:0] R/W R/W Description Software reset control register Description Reset Value Initial State - Software controlled reset setting code NOTE: SOFTRESET command is 0xA3. When this register was set with the value of 0xXXXX_XXA3 the soft-reset is activated. 33-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. |
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